Chad Rosier 27c352d26d [AArch64] Refactor AArch64FrameLowering::emitPrologue. NFC. ... http://reviews.llvm.org/D18125 Patch by Aditya Kumar. llvm-svn: 263461		2016-03-14 18:24:34 +00:00
..
AArch64	AArch64: remove CRC feature from Cyclone.	2016-02-24 18:10:17 +00:00
AMDGPU	[AMDGPU] Assembler: SOP* instruction fixes	2016-03-14 11:17:19 +00:00
ARM	ARM: Support relative references using the PREL31 symbol variant.	2016-03-10 19:30:18 +00:00
AsmParser	AsmParser: Fix nested .irp/.irpc	2016-03-01 08:18:28 +00:00
COFF	[codeview] Dump def range lengths in hex	2016-02-11 23:40:14 +00:00
Disassembler	[AMDGPU] Fix VOPC instruction operand namings	2016-03-11 14:53:28 +00:00
ELF	Accept subtractions involving a weak symbol.	2016-01-20 18:57:48 +00:00
Hexagon	[Hexagon] As a size optimization, not lazy extending TPREL or DTPREL variants since they're usually in range.	2016-02-29 21:21:56 +00:00
MachO	[AArch64] Refactor AArch64FrameLowering::emitPrologue. NFC.	2016-03-14 18:24:34 +00:00
Markup	…
Mips	[mips] Range check uimm16_64	2016-03-14 12:44:44 +00:00
PowerPC	[Power9] Implement new vsx instructions: load, store instructions for vector and scalar	2016-03-08 03:49:13 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Sort relocs to avoid code corruption by linker optimization	2015-12-16 18:12:40 +00:00
X86	[X86] Make X86MCCodeEmitter::DetermineREXPrefix locate operands more like how VEX prefix handling does.	2016-03-02 07:32:43 +00:00