forked from OSchip/llvm-project
118 lines
3.7 KiB
YAML
118 lines
3.7 KiB
YAML
# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - 2>&1 | FileCheck %s
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--- |
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define void @test_load(i8* %addr) {
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entry:
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ret void
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}
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define void @test_store(i8* %addr) {
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entry:
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ret void
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}
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...
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---
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name: test_load
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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- { id: 8, class: _ }
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body: |
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bb.0.entry:
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liveins: %x0, %x1, %x2, %x3
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; CHECK-LABEL: name: test_load
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%0(p0) = COPY %x0
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; CHECK: [[BIT8:%[0-9]+]](s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
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; CHECK: %1(s1) = G_TRUNC [[BIT8]]
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%1(s1) = G_LOAD %0 :: (load 1 from %ir.addr)
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; CHECK: %2(s8) = G_LOAD %0(p0) :: (load 1 from %ir.addr)
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%2(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
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; CHECK: %3(s16) = G_LOAD %0(p0) :: (load 2 from %ir.addr)
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%3(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
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; CHECK: %4(s32) = G_LOAD %0(p0) :: (load 4 from %ir.addr)
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%4(s32) = G_LOAD %0 :: (load 4 from %ir.addr)
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; CHECK: %5(s64) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
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%5(s64) = G_LOAD %0 :: (load 8 from %ir.addr)
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; CHECK: %6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
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%6(p0) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
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; CHECK: %7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
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%7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr)
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; CHECK: [[OFFSET0:%[0-9]+]](s64) = G_CONSTANT i64 0
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; CHECK: [[GEP0:%[0-9]+]](p0) = G_GEP %0, [[OFFSET0]](s64)
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; CHECK: [[LOAD0:%[0-9]+]](s64) = G_LOAD [[GEP0]](p0) :: (load 16 from %ir.addr)
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; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 8
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; CHECK: [[GEP1:%[0-9]+]](p0) = G_GEP %0, [[OFFSET1]](s64)
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; CHECK: [[LOAD1:%[0-9]+]](s64) = G_LOAD [[GEP1]](p0) :: (load 16 from %ir.addr)
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; CHECK: %8(s128) = G_SEQUENCE [[LOAD0]](s64), 0, [[LOAD1]](s64), 64
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%8(s128) = G_LOAD %0(p0) :: (load 16 from %ir.addr)
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...
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---
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name: test_store
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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- { id: 7, class: _ }
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body: |
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bb.0.entry:
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liveins: %x0, %x1, %x2, %x3
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; CHECK-LABEL: name: test_store
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%0(p0) = COPY %x0
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%1(s32) = COPY %w1
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; CHECK: [[BIT8:%[0-9]+]](s8) = G_ANYEXT %2(s1)
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; CHECK: G_STORE [[BIT8]](s8), %0(p0) :: (store 1 into %ir.addr)
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%2(s1) = G_TRUNC %1
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G_STORE %2, %0 :: (store 1 into %ir.addr)
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; CHECK: G_STORE %3(s8), %0(p0) :: (store 1 into %ir.addr)
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%3(s8) = G_TRUNC %1
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G_STORE %3, %0 :: (store 1 into %ir.addr)
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; CHECK: G_STORE %4(s16), %0(p0) :: (store 2 into %ir.addr)
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%4(s16) = G_TRUNC %1
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G_STORE %4, %0 :: (store 2 into %ir.addr)
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; CHECK: G_STORE %1(s32), %0(p0) :: (store 4 into %ir.addr)
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G_STORE %1, %0 :: (store 4 into %ir.addr)
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; CHECK: G_STORE %5(s64), %0(p0) :: (store 8 into %ir.addr)
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%5(s64) = G_PTRTOINT %0(p0)
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G_STORE %5, %0 :: (store 8 into %ir.addr)
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; CHECK: G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr)
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G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr)
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; CHECK: [[OFFSET0:%[0-9]+]](s64) = G_CONSTANT i64 0
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; CHECK: [[GEP0:%[0-9]+]](p0) = G_GEP %0, [[OFFSET0]](s64)
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; CHECK: G_STORE %5(s64), [[GEP0]](p0) :: (store 16 into %ir.addr)
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; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 8
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; CHECK: [[GEP1:%[0-9]+]](p0) = G_GEP %0, [[OFFSET1]](s64)
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; CHECK: G_STORE %6(s64), [[GEP1]](p0) :: (store 16 into %ir.addr)
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%6(s64) = G_PTRTOINT %0(p0)
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%7(s128) = G_SEQUENCE %5, 0, %6, 64
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G_STORE %7, %0 :: (store 16 into %ir.addr)
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...
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