forked from OSchip/llvm-project
147 lines
5.3 KiB
LLVM
147 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O1 -mtriple=x86_64-unknown-unknown -o - | FileCheck %s
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; We used to assert on widening the SMULFIX/UMULFIX/SMULFIXSAT node result,
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; so primiary goal with the test is to see that we support legalization for
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; such vectors.
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declare <4 x i16> @llvm.smul.fix.v4i16(<4 x i16>, <4 x i16>, i32 immarg)
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declare <4 x i16> @llvm.umul.fix.v4i16(<4 x i16>, <4 x i16>, i32 immarg)
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declare <4 x i16> @llvm.smul.fix.sat.v4i16(<4 x i16>, <4 x i16>, i32 immarg)
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declare <4 x i16> @llvm.umul.fix.sat.v4i16(<4 x i16>, <4 x i16>, i32 immarg)
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define <4 x i16> @smulfix(<4 x i16> %a) {
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; CHECK-LABEL: smulfix:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movdqa {{.*#+}} xmm1 = <1,2,3,4,u,u,u,u>
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; CHECK-NEXT: movdqa %xmm0, %xmm2
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; CHECK-NEXT: pmullw %xmm1, %xmm2
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; CHECK-NEXT: psrlw $15, %xmm2
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; CHECK-NEXT: pmulhw %xmm1, %xmm0
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; CHECK-NEXT: psllw $1, %xmm0
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; CHECK-NEXT: por %xmm2, %xmm0
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; CHECK-NEXT: retq
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%t = call <4 x i16> @llvm.smul.fix.v4i16(<4 x i16> <i16 1, i16 2, i16 3, i16 4>, <4 x i16> %a, i32 15)
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ret <4 x i16> %t
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}
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define <4 x i16> @umulfix(<4 x i16> %a) {
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; CHECK-LABEL: umulfix:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movdqa {{.*#+}} xmm1 = <1,2,3,4,u,u,u,u>
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; CHECK-NEXT: movdqa %xmm0, %xmm2
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; CHECK-NEXT: pmullw %xmm1, %xmm2
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; CHECK-NEXT: psrlw $15, %xmm2
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; CHECK-NEXT: pmulhuw %xmm1, %xmm0
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; CHECK-NEXT: psllw $1, %xmm0
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; CHECK-NEXT: por %xmm2, %xmm0
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; CHECK-NEXT: retq
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%t = call <4 x i16> @llvm.umul.fix.v4i16(<4 x i16> <i16 1, i16 2, i16 3, i16 4>, <4 x i16> %a, i32 15)
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ret <4 x i16> %t
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}
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define <4 x i16> @smulfixsat(<4 x i16> %a) {
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; CHECK-LABEL: smulfixsat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pextrw $2, %xmm0, %eax
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; CHECK-NEXT: cwtl
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; CHECK-NEXT: leal (%rax,%rax,2), %ecx
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; CHECK-NEXT: movl %ecx, %edx
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; CHECK-NEXT: shrl $16, %edx
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; CHECK-NEXT: shldw $1, %cx, %dx
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; CHECK-NEXT: sarl $16, %ecx
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; CHECK-NEXT: cmpl $16383, %ecx # imm = 0x3FFF
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; CHECK-NEXT: movl $32767, %r8d # imm = 0x7FFF
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; CHECK-NEXT: cmovgl %r8d, %edx
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; CHECK-NEXT: cmpl $-16384, %ecx # imm = 0xC000
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; CHECK-NEXT: movl $32768, %ecx # imm = 0x8000
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; CHECK-NEXT: cmovll %ecx, %edx
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; CHECK-NEXT: pextrw $1, %xmm0, %esi
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; CHECK-NEXT: movswl %si, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shrl $15, %eax
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; CHECK-NEXT: leal (%rdi,%rdi), %esi
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; CHECK-NEXT: shrdw $15, %ax, %si
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; CHECK-NEXT: sarl $15, %edi
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; CHECK-NEXT: cmpl $16383, %edi # imm = 0x3FFF
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; CHECK-NEXT: cmovgl %r8d, %esi
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; CHECK-NEXT: cmpl $-16384, %edi # imm = 0xC000
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; CHECK-NEXT: cmovll %ecx, %esi
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; CHECK-NEXT: movd %xmm0, %eax
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; CHECK-NEXT: cwtl
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; CHECK-NEXT: movl %eax, %edi
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; CHECK-NEXT: shrl $16, %edi
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; CHECK-NEXT: shldw $1, %ax, %di
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; CHECK-NEXT: sarl $16, %eax
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; CHECK-NEXT: cmpl $16383, %eax # imm = 0x3FFF
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; CHECK-NEXT: cmovgl %r8d, %edi
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; CHECK-NEXT: cmpl $-16384, %eax # imm = 0xC000
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; CHECK-NEXT: cmovll %ecx, %edi
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pinsrw $0, %edi, %xmm1
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; CHECK-NEXT: pinsrw $1, %esi, %xmm1
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; CHECK-NEXT: pinsrw $2, %edx, %xmm1
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; CHECK-NEXT: pextrw $3, %xmm0, %eax
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; CHECK-NEXT: cwtl
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: shrl $14, %edx
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; CHECK-NEXT: leal (,%rax,4), %esi
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; CHECK-NEXT: shrdw $15, %dx, %si
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; CHECK-NEXT: sarl $14, %eax
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; CHECK-NEXT: cmpl $16383, %eax # imm = 0x3FFF
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; CHECK-NEXT: cmovgl %r8d, %esi
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; CHECK-NEXT: cmpl $-16384, %eax # imm = 0xC000
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; CHECK-NEXT: cmovll %ecx, %esi
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; CHECK-NEXT: pinsrw $3, %esi, %xmm1
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: retq
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%t = call <4 x i16> @llvm.smul.fix.sat.v4i16(<4 x i16> <i16 1, i16 2, i16 3, i16 4>, <4 x i16> %a, i32 15)
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ret <4 x i16> %t
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}
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define <4 x i16> @umulfixsat(<4 x i16> %a) {
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; CHECK-LABEL: umulfixsat:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pextrw $2, %xmm0, %eax
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; CHECK-NEXT: leal (%rax,%rax,2), %eax
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: shrl $16, %edx
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; CHECK-NEXT: movl %edx, %ecx
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; CHECK-NEXT: shldw $1, %ax, %cx
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; CHECK-NEXT: cmpl $32767, %edx # imm = 0x7FFF
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; CHECK-NEXT: movl $65535, %eax # imm = 0xFFFF
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; CHECK-NEXT: cmoval %eax, %ecx
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; CHECK-NEXT: pextrw $1, %xmm0, %edx
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; CHECK-NEXT: addl %edx, %edx
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; CHECK-NEXT: movl %edx, %esi
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; CHECK-NEXT: shrl $16, %esi
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; CHECK-NEXT: movl %esi, %edi
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; CHECK-NEXT: shldw $1, %dx, %di
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; CHECK-NEXT: cmpl $32767, %esi # imm = 0x7FFF
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; CHECK-NEXT: cmoval %eax, %edi
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; CHECK-NEXT: movd %xmm0, %edx
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; CHECK-NEXT: xorl %esi, %esi
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; CHECK-NEXT: shldw $1, %dx, %si
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; CHECK-NEXT: movl $32767, %edx # imm = 0x7FFF
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; CHECK-NEXT: negl %edx
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; CHECK-NEXT: cmoval %eax, %esi
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; CHECK-NEXT: pxor %xmm1, %xmm1
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; CHECK-NEXT: pinsrw $0, %esi, %xmm1
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; CHECK-NEXT: pinsrw $1, %edi, %xmm1
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; CHECK-NEXT: pinsrw $2, %ecx, %xmm1
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; CHECK-NEXT: pextrw $3, %xmm0, %ecx
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; CHECK-NEXT: shll $2, %ecx
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; CHECK-NEXT: movl %ecx, %edx
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; CHECK-NEXT: shrl $16, %edx
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; CHECK-NEXT: movl %edx, %esi
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; CHECK-NEXT: shldw $1, %cx, %si
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; CHECK-NEXT: cmpl $32767, %edx # imm = 0x7FFF
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; CHECK-NEXT: cmoval %eax, %esi
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; CHECK-NEXT: pinsrw $3, %esi, %xmm1
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: retq
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%t = call <4 x i16> @llvm.umul.fix.sat.v4i16(<4 x i16> <i16 1, i16 2, i16 3, i16 4>, <4 x i16> %a, i32 15)
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ret <4 x i16> %t
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}
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