forked from OSchip/llvm-project
40 lines
1.4 KiB
LLVM
40 lines
1.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare i32 @llvm.r600.read.tidig.x() #1
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; SI-LABEL: {{^}}v_cnd_nan_nosgpr:
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; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}}
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; SI-DAG: v{{[0-9]}}
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; All nan values are converted to 0xffffffff
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; SI: s_endpgm
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define void @v_cnd_nan_nosgpr(float addrspace(1)* %out, i32 %c, float addrspace(1)* %fptr) #0 {
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%idx = call i32 @llvm.r600.read.tidig.x() #1
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%f.gep = getelementptr float, float addrspace(1)* %fptr, i32 %idx
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%f = load float, float addrspace(1)* %fptr
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%setcc = icmp ne i32 %c, 0
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%select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
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store float %select, float addrspace(1)* %out
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ret void
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}
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; This requires slightly trickier SGPR operand legalization since the
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; single constant bus SGPR usage is the last operand, and it should
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; never be moved.
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; SI-LABEL: {{^}}v_cnd_nan:
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; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}}
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; SI-DAG: v{{[0-9]}}
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; All nan values are converted to 0xffffffff
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; SI: s_endpgm
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define void @v_cnd_nan(float addrspace(1)* %out, i32 %c, float %f) #0 {
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%setcc = icmp ne i32 %c, 0
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%select = select i1 %setcc, float 0xFFFFFFFFE0000000, float %f
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store float %select, float addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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