forked from OSchip/llvm-project
99f35eab45
This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. llvm-svn: 133105 |
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.. | ||
TargetInfo | ||
CMakeLists.txt | ||
Makefile | ||
README.txt | ||
XCore.h | ||
XCore.td | ||
XCoreAsmPrinter.cpp | ||
XCoreCallingConv.td | ||
XCoreFrameLowering.cpp | ||
XCoreFrameLowering.h | ||
XCoreISelDAGToDAG.cpp | ||
XCoreISelLowering.cpp | ||
XCoreISelLowering.h | ||
XCoreInstrFormats.td | ||
XCoreInstrInfo.cpp | ||
XCoreInstrInfo.h | ||
XCoreInstrInfo.td | ||
XCoreMCAsmInfo.cpp | ||
XCoreMCAsmInfo.h | ||
XCoreMachineFunctionInfo.h | ||
XCoreRegisterInfo.cpp | ||
XCoreRegisterInfo.h | ||
XCoreRegisterInfo.td | ||
XCoreSelectionDAGInfo.cpp | ||
XCoreSelectionDAGInfo.h | ||
XCoreSubtarget.cpp | ||
XCoreSubtarget.h | ||
XCoreTargetMachine.cpp | ||
XCoreTargetMachine.h | ||
XCoreTargetObjectFile.cpp | ||
XCoreTargetObjectFile.h |
README.txt
To-do ----- * Instruction encodings * Tailcalls * Investigate loop alignment * Add builtins