forked from OSchip/llvm-project
591 lines
24 KiB
C++
591 lines
24 KiB
C++
//===-- XCoreFrameLowering.cpp - Frame info for XCore Target --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains XCore frame information that doesn't fit anywhere else
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// cleanly...
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//
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//===----------------------------------------------------------------------===//
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#include "XCoreFrameLowering.h"
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#include "XCore.h"
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#include "XCoreInstrInfo.h"
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#include "XCoreMachineFunctionInfo.h"
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#include "XCoreSubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetOptions.h"
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#include <algorithm> // std::sort
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using namespace llvm;
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static const unsigned FramePtr = XCore::R10;
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static const int MaxImmU16 = (1<<16) - 1;
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// helper functions. FIXME: Eliminate.
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static inline bool isImmU6(unsigned val) {
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return val < (1 << 6);
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}
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static inline bool isImmU16(unsigned val) {
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return val < (1 << 16);
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}
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// Helper structure with compare function for handling stack slots.
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namespace {
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struct StackSlotInfo {
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int FI;
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int Offset;
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unsigned Reg;
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StackSlotInfo(int f, int o, int r) : FI(f), Offset(o), Reg(r){};
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};
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} // end anonymous namespace
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static bool CompareSSIOffset(const StackSlotInfo& a, const StackSlotInfo& b) {
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return a.Offset < b.Offset;
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}
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static void EmitDefCfaRegister(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &dl, const TargetInstrInfo &TII,
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MachineFunction &MF, unsigned DRegNum) {
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unsigned CFIIndex = MF.addFrameInst(
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MCCFIInstruction::createDefCfaRegister(nullptr, DRegNum));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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static void EmitDefCfaOffset(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &dl, const TargetInstrInfo &TII,
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int Offset) {
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MachineFunction &MF = *MBB.getParent();
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unsigned CFIIndex =
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MF.addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -Offset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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static void EmitCfiOffset(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, const DebugLoc &dl,
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const TargetInstrInfo &TII, unsigned DRegNum,
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int Offset) {
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MachineFunction &MF = *MBB.getParent();
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unsigned CFIIndex = MF.addFrameInst(
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MCCFIInstruction::createOffset(nullptr, DRegNum, Offset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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/// The SP register is moved in steps of 'MaxImmU16' towards the bottom of the
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/// frame. During these steps, it may be necessary to spill registers.
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/// IfNeededExtSP emits the necessary EXTSP instructions to move the SP only
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/// as far as to make 'OffsetFromBottom' reachable using an STWSP_lru6.
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/// \param OffsetFromTop the spill offset from the top of the frame.
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/// \param [in,out] Adjusted the current SP offset from the top of the frame.
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static void IfNeededExtSP(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, const DebugLoc &dl,
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const TargetInstrInfo &TII, int OffsetFromTop,
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int &Adjusted, int FrameSize, bool emitFrameMoves) {
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while (OffsetFromTop > Adjusted) {
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assert(Adjusted < FrameSize && "OffsetFromTop is beyond FrameSize");
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int remaining = FrameSize - Adjusted;
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int OpImm = (remaining > MaxImmU16) ? MaxImmU16 : remaining;
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int Opcode = isImmU6(OpImm) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
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Adjusted += OpImm;
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if (emitFrameMoves)
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EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4);
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}
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}
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/// The SP register is moved in steps of 'MaxImmU16' towards the top of the
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/// frame. During these steps, it may be necessary to re-load registers.
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/// IfNeededLDAWSP emits the necessary LDAWSP instructions to move the SP only
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/// as far as to make 'OffsetFromTop' reachable using an LDAWSP_lru6.
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/// \param OffsetFromTop the spill offset from the top of the frame.
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/// \param [in,out] RemainingAdj the current SP offset from the top of the
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/// frame.
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static void IfNeededLDAWSP(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, const DebugLoc &dl,
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const TargetInstrInfo &TII, int OffsetFromTop,
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int &RemainingAdj) {
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while (OffsetFromTop < RemainingAdj - MaxImmU16) {
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assert(RemainingAdj && "OffsetFromTop is beyond FrameSize");
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int OpImm = (RemainingAdj > MaxImmU16) ? MaxImmU16 : RemainingAdj;
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int Opcode = isImmU6(OpImm) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
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RemainingAdj -= OpImm;
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}
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}
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/// Creates an ordered list of registers that are spilled
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/// during the emitPrologue/emitEpilogue.
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/// Registers are ordered according to their frame offset.
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/// As offsets are negative, the largest offsets will be first.
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static void GetSpillList(SmallVectorImpl<StackSlotInfo> &SpillList,
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MachineFrameInfo &MFI, XCoreFunctionInfo *XFI,
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bool fetchLR, bool fetchFP) {
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if (fetchLR) {
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int Offset = MFI.getObjectOffset(XFI->getLRSpillSlot());
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SpillList.push_back(StackSlotInfo(XFI->getLRSpillSlot(),
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Offset,
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XCore::LR));
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}
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if (fetchFP) {
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int Offset = MFI.getObjectOffset(XFI->getFPSpillSlot());
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SpillList.push_back(StackSlotInfo(XFI->getFPSpillSlot(),
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Offset,
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FramePtr));
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}
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llvm::sort(SpillList, CompareSSIOffset);
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}
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/// Creates an ordered list of EH info register 'spills'.
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/// These slots are only used by the unwinder and calls to llvm.eh.return().
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/// Registers are ordered according to their frame offset.
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/// As offsets are negative, the largest offsets will be first.
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static void GetEHSpillList(SmallVectorImpl<StackSlotInfo> &SpillList,
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MachineFrameInfo &MFI, XCoreFunctionInfo *XFI,
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const Constant *PersonalityFn,
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const TargetLowering *TL) {
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assert(XFI->hasEHSpillSlot() && "There are no EH register spill slots");
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const int *EHSlot = XFI->getEHSpillSlot();
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SpillList.push_back(
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StackSlotInfo(EHSlot[0], MFI.getObjectOffset(EHSlot[0]),
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TL->getExceptionPointerRegister(PersonalityFn)));
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SpillList.push_back(
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StackSlotInfo(EHSlot[0], MFI.getObjectOffset(EHSlot[1]),
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TL->getExceptionSelectorRegister(PersonalityFn)));
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llvm::sort(SpillList, CompareSSIOffset);
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}
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static MachineMemOperand *getFrameIndexMMO(MachineBasicBlock &MBB,
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int FrameIndex,
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MachineMemOperand::Flags flags) {
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MachineFunction *MF = MBB.getParent();
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const MachineFrameInfo &MFI = MF->getFrameInfo();
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MachineMemOperand *MMO = MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(*MF, FrameIndex), flags,
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MFI.getObjectSize(FrameIndex), MFI.getObjectAlignment(FrameIndex));
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return MMO;
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}
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/// Restore clobbered registers with their spill slot value.
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/// The SP will be adjusted at the same time, thus the SpillList must be ordered
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/// with the largest (negative) offsets first.
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static void RestoreSpillList(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &dl, const TargetInstrInfo &TII,
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int &RemainingAdj,
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SmallVectorImpl<StackSlotInfo> &SpillList) {
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for (unsigned i = 0, e = SpillList.size(); i != e; ++i) {
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assert(SpillList[i].Offset % 4 == 0 && "Misaligned stack offset");
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assert(SpillList[i].Offset <= 0 && "Unexpected positive stack offset");
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int OffsetFromTop = - SpillList[i].Offset/4;
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IfNeededLDAWSP(MBB, MBBI, dl, TII, OffsetFromTop, RemainingAdj);
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int Offset = RemainingAdj - OffsetFromTop;
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int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
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.addImm(Offset)
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.addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI,
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MachineMemOperand::MOLoad));
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}
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}
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//===----------------------------------------------------------------------===//
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// XCoreFrameLowering:
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//===----------------------------------------------------------------------===//
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XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti)
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0) {
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// Do nothing
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}
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bool XCoreFrameLowering::hasFP(const MachineFunction &MF) const {
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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MF.getFrameInfo().hasVarSizedObjects();
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}
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void XCoreFrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MachineModuleInfo *MMI = &MF.getMMI();
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const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo();
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const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo();
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XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
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// Debug location must be unknown since the first debug location is used
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// to determine the end of the prologue.
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DebugLoc dl;
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if (MFI.getMaxAlignment() > getStackAlignment())
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report_fatal_error("emitPrologue unsupported alignment: "
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+ Twine(MFI.getMaxAlignment()));
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const AttributeList &PAL = MF.getFunction().getAttributes();
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if (PAL.hasAttrSomewhere(Attribute::Nest))
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BuildMI(MBB, MBBI, dl, TII.get(XCore::LDWSP_ru6), XCore::R11).addImm(0);
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// FIX: Needs addMemOperand() but can't use getFixedStack() or getStack().
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// Work out frame sizes.
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// We will adjust the SP in stages towards the final FrameSize.
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assert(MFI.getStackSize()%4 == 0 && "Misaligned frame size");
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const int FrameSize = MFI.getStackSize() / 4;
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int Adjusted = 0;
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bool saveLR = XFI->hasLRSpillSlot();
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bool UseENTSP = saveLR && FrameSize
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&& (MFI.getObjectOffset(XFI->getLRSpillSlot()) == 0);
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if (UseENTSP)
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saveLR = false;
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bool FP = hasFP(MF);
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bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(MF);
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if (UseENTSP) {
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// Allocate space on the stack at the same time as saving LR.
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Adjusted = (FrameSize > MaxImmU16) ? MaxImmU16 : FrameSize;
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int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
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MBB.addLiveIn(XCore::LR);
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
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MIB.addImm(Adjusted);
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MIB->addRegisterKilled(XCore::LR, MF.getSubtarget().getRegisterInfo(),
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true);
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if (emitFrameMoves) {
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EmitDefCfaOffset(MBB, MBBI, dl, TII, Adjusted*4);
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unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true);
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EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, 0);
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}
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}
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// If necessary, save LR and FP to the stack, as we EXTSP.
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SmallVector<StackSlotInfo,2> SpillList;
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GetSpillList(SpillList, MFI, XFI, saveLR, FP);
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// We want the nearest (negative) offsets first, so reverse list.
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std::reverse(SpillList.begin(), SpillList.end());
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for (unsigned i = 0, e = SpillList.size(); i != e; ++i) {
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assert(SpillList[i].Offset % 4 == 0 && "Misaligned stack offset");
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assert(SpillList[i].Offset <= 0 && "Unexpected positive stack offset");
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int OffsetFromTop = - SpillList[i].Offset/4;
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IfNeededExtSP(MBB, MBBI, dl, TII, OffsetFromTop, Adjusted, FrameSize,
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emitFrameMoves);
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int Offset = Adjusted - OffsetFromTop;
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int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
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MBB.addLiveIn(SpillList[i].Reg);
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BuildMI(MBB, MBBI, dl, TII.get(Opcode))
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.addReg(SpillList[i].Reg, RegState::Kill)
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.addImm(Offset)
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.addMemOperand(getFrameIndexMMO(MBB, SpillList[i].FI,
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MachineMemOperand::MOStore));
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if (emitFrameMoves) {
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unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true);
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EmitCfiOffset(MBB, MBBI, dl, TII, DRegNum, SpillList[i].Offset);
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}
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}
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// Complete any remaining Stack adjustment.
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IfNeededExtSP(MBB, MBBI, dl, TII, FrameSize, Adjusted, FrameSize,
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emitFrameMoves);
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assert(Adjusted==FrameSize && "IfNeededExtSP has not completed adjustment");
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if (FP) {
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// Set the FP from the SP.
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BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
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if (emitFrameMoves)
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EmitDefCfaRegister(MBB, MBBI, dl, TII, MF,
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MRI->getDwarfRegNum(FramePtr, true));
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}
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if (emitFrameMoves) {
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// Frame moves for callee saved.
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for (const auto &SpillLabel : XFI->getSpillLabels()) {
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MachineBasicBlock::iterator Pos = SpillLabel.first;
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++Pos;
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const CalleeSavedInfo &CSI = SpillLabel.second;
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int Offset = MFI.getObjectOffset(CSI.getFrameIdx());
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unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true);
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EmitCfiOffset(MBB, Pos, dl, TII, DRegNum, Offset);
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}
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if (XFI->hasEHSpillSlot()) {
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// The unwinder requires stack slot & CFI offsets for the exception info.
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// We do not save/spill these registers.
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const Function *Fn = &MF.getFunction();
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const Constant *PersonalityFn =
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Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr;
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SmallVector<StackSlotInfo, 2> SpillList;
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GetEHSpillList(SpillList, MFI, XFI, PersonalityFn,
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MF.getSubtarget().getTargetLowering());
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assert(SpillList.size()==2 && "Unexpected SpillList size");
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EmitCfiOffset(MBB, MBBI, dl, TII,
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MRI->getDwarfRegNum(SpillList[0].Reg, true),
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SpillList[0].Offset);
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EmitCfiOffset(MBB, MBBI, dl, TII,
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MRI->getDwarfRegNum(SpillList[1].Reg, true),
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SpillList[1].Offset);
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}
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}
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}
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void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo();
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XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
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DebugLoc dl = MBBI->getDebugLoc();
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unsigned RetOpcode = MBBI->getOpcode();
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// Work out frame sizes.
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// We will adjust the SP in stages towards the final FrameSize.
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int RemainingAdj = MFI.getStackSize();
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assert(RemainingAdj%4 == 0 && "Misaligned frame size");
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RemainingAdj /= 4;
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if (RetOpcode == XCore::EH_RETURN) {
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// 'Restore' the exception info the unwinder has placed into the stack
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// slots.
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const Function *Fn = &MF.getFunction();
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const Constant *PersonalityFn =
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Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr;
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SmallVector<StackSlotInfo, 2> SpillList;
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GetEHSpillList(SpillList, MFI, XFI, PersonalityFn,
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MF.getSubtarget().getTargetLowering());
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RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
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// Return to the landing pad.
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unsigned EhStackReg = MBBI->getOperand(0).getReg();
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unsigned EhHandlerReg = MBBI->getOperand(1).getReg();
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BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(EhStackReg);
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BuildMI(MBB, MBBI, dl, TII.get(XCore::BAU_1r)).addReg(EhHandlerReg);
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MBB.erase(MBBI); // Erase the previous return instruction.
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return;
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}
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bool restoreLR = XFI->hasLRSpillSlot();
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bool UseRETSP = restoreLR && RemainingAdj
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&& (MFI.getObjectOffset(XFI->getLRSpillSlot()) == 0);
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if (UseRETSP)
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restoreLR = false;
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bool FP = hasFP(MF);
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if (FP) // Restore the stack pointer.
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BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
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// If necessary, restore LR and FP from the stack, as we EXTSP.
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SmallVector<StackSlotInfo,2> SpillList;
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GetSpillList(SpillList, MFI, XFI, restoreLR, FP);
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RestoreSpillList(MBB, MBBI, dl, TII, RemainingAdj, SpillList);
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if (RemainingAdj) {
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// Complete all but one of the remaining Stack adjustments.
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IfNeededLDAWSP(MBB, MBBI, dl, TII, 0, RemainingAdj);
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if (UseRETSP) {
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// Fold prologue into return instruction
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assert(RetOpcode == XCore::RETSP_u6
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|| RetOpcode == XCore::RETSP_lu6);
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int Opcode = isImmU6(RemainingAdj) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode))
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.addImm(RemainingAdj);
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for (unsigned i = 3, e = MBBI->getNumOperands(); i < e; ++i)
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MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
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MBB.erase(MBBI); // Erase the previous return instruction.
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} else {
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int Opcode = isImmU6(RemainingAdj) ? XCore::LDAWSP_ru6 :
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XCore::LDAWSP_lru6;
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BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(RemainingAdj);
|
|
// Don't erase the return instruction.
|
|
}
|
|
} // else Don't erase the return instruction.
|
|
}
|
|
|
|
bool XCoreFrameLowering::
|
|
spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI,
|
|
const TargetRegisterInfo *TRI) const {
|
|
if (CSI.empty())
|
|
return true;
|
|
|
|
MachineFunction *MF = MBB.getParent();
|
|
const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
|
|
XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();
|
|
bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
|
|
|
|
DebugLoc DL;
|
|
if (MI != MBB.end() && !MI->isDebugInstr())
|
|
DL = MI->getDebugLoc();
|
|
|
|
for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
|
|
it != CSI.end(); ++it) {
|
|
unsigned Reg = it->getReg();
|
|
assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&
|
|
"LR & FP are always handled in emitPrologue");
|
|
|
|
// Add the callee-saved register as live-in. It's killed at the spill.
|
|
MBB.addLiveIn(Reg);
|
|
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
|
|
TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI);
|
|
if (emitFrameMoves) {
|
|
auto Store = MI;
|
|
--Store;
|
|
XFI->getSpillLabels().push_back(std::make_pair(Store, *it));
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool XCoreFrameLowering::
|
|
restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
std::vector<CalleeSavedInfo> &CSI,
|
|
const TargetRegisterInfo *TRI) const{
|
|
MachineFunction *MF = MBB.getParent();
|
|
const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
|
|
bool AtStart = MI == MBB.begin();
|
|
MachineBasicBlock::iterator BeforeI = MI;
|
|
if (!AtStart)
|
|
--BeforeI;
|
|
for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
|
|
it != CSI.end(); ++it) {
|
|
unsigned Reg = it->getReg();
|
|
assert(Reg != XCore::LR && !(Reg == XCore::R10 && hasFP(*MF)) &&
|
|
"LR & FP are always handled in emitEpilogue");
|
|
|
|
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
|
|
TII.loadRegFromStackSlot(MBB, MI, Reg, it->getFrameIdx(), RC, TRI);
|
|
assert(MI != MBB.begin() &&
|
|
"loadRegFromStackSlot didn't insert any code!");
|
|
// Insert in reverse order. loadRegFromStackSlot can insert multiple
|
|
// instructions.
|
|
if (AtStart)
|
|
MI = MBB.begin();
|
|
else {
|
|
MI = BeforeI;
|
|
++MI;
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
// This function eliminates ADJCALLSTACKDOWN,
|
|
// ADJCALLSTACKUP pseudo instructions
|
|
MachineBasicBlock::iterator XCoreFrameLowering::eliminateCallFramePseudoInstr(
|
|
MachineFunction &MF, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const {
|
|
const XCoreInstrInfo &TII = *MF.getSubtarget<XCoreSubtarget>().getInstrInfo();
|
|
if (!hasReservedCallFrame(MF)) {
|
|
// Turn the adjcallstackdown instruction into 'extsp <amt>' and the
|
|
// adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
|
|
MachineInstr &Old = *I;
|
|
uint64_t Amount = Old.getOperand(0).getImm();
|
|
if (Amount != 0) {
|
|
// We need to keep the stack aligned properly. To do this, we round the
|
|
// amount of space needed for the outgoing arguments up to the next
|
|
// alignment boundary.
|
|
unsigned Align = getStackAlignment();
|
|
Amount = (Amount+Align-1)/Align*Align;
|
|
|
|
assert(Amount%4 == 0);
|
|
Amount /= 4;
|
|
|
|
bool isU6 = isImmU6(Amount);
|
|
if (!isU6 && !isImmU16(Amount)) {
|
|
// FIX could emit multiple instructions in this case.
|
|
#ifndef NDEBUG
|
|
errs() << "eliminateCallFramePseudoInstr size too big: "
|
|
<< Amount << "\n";
|
|
#endif
|
|
llvm_unreachable(nullptr);
|
|
}
|
|
|
|
MachineInstr *New;
|
|
if (Old.getOpcode() == XCore::ADJCALLSTACKDOWN) {
|
|
int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
|
|
New = BuildMI(MF, Old.getDebugLoc(), TII.get(Opcode)).addImm(Amount);
|
|
} else {
|
|
assert(Old.getOpcode() == XCore::ADJCALLSTACKUP);
|
|
int Opcode = isU6 ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
|
|
New = BuildMI(MF, Old.getDebugLoc(), TII.get(Opcode), XCore::SP)
|
|
.addImm(Amount);
|
|
}
|
|
|
|
// Replace the pseudo instruction with a new instruction...
|
|
MBB.insert(I, New);
|
|
}
|
|
}
|
|
|
|
return MBB.erase(I);
|
|
}
|
|
|
|
void XCoreFrameLowering::determineCalleeSaves(MachineFunction &MF,
|
|
BitVector &SavedRegs,
|
|
RegScavenger *RS) const {
|
|
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
|
|
|
|
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
|
|
|
|
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
bool LRUsed = MRI.isPhysRegModified(XCore::LR);
|
|
|
|
if (!LRUsed && !MF.getFunction().isVarArg() &&
|
|
MF.getFrameInfo().estimateStackSize(MF))
|
|
// If we need to extend the stack it is more efficient to use entsp / retsp.
|
|
// We force the LR to be saved so these instructions are used.
|
|
LRUsed = true;
|
|
|
|
if (MF.callsUnwindInit() || MF.callsEHReturn()) {
|
|
// The unwinder expects to find spill slots for the exception info regs R0
|
|
// & R1. These are used during llvm.eh.return() to 'restore' the exception
|
|
// info. N.B. we do not spill or restore R0, R1 during normal operation.
|
|
XFI->createEHSpillSlot(MF);
|
|
// As we will have a stack, we force the LR to be saved.
|
|
LRUsed = true;
|
|
}
|
|
|
|
if (LRUsed) {
|
|
// We will handle the LR in the prologue/epilogue
|
|
// and allocate space on the stack ourselves.
|
|
SavedRegs.reset(XCore::LR);
|
|
XFI->createLRSpillSlot(MF);
|
|
}
|
|
|
|
if (hasFP(MF))
|
|
// A callee save register is used to hold the FP.
|
|
// This needs saving / restoring in the epilogue / prologue.
|
|
XFI->createFPSpillSlot(MF);
|
|
}
|
|
|
|
void XCoreFrameLowering::
|
|
processFunctionBeforeFrameFinalized(MachineFunction &MF,
|
|
RegScavenger *RS) const {
|
|
assert(RS && "requiresRegisterScavenging failed");
|
|
MachineFrameInfo &MFI = MF.getFrameInfo();
|
|
const TargetRegisterClass &RC = XCore::GRRegsRegClass;
|
|
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
|
|
XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
|
|
// Reserve slots close to SP or frame pointer for Scavenging spills.
|
|
// When using SP for small frames, we don't need any scratch registers.
|
|
// When using SP for large frames, we may need 2 scratch registers.
|
|
// When using FP, for large or small frames, we may need 1 scratch register.
|
|
unsigned Size = TRI.getSpillSize(RC);
|
|
unsigned Align = TRI.getSpillAlignment(RC);
|
|
if (XFI->isLargeFrame(MF) || hasFP(MF))
|
|
RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
|
|
if (XFI->isLargeFrame(MF) && !hasFP(MF))
|
|
RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
|
|
}
|