llvm-project/llvm/test/CodeGen/ARM/ParallelDSP
QingShan Zhang bb8d540010 [TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel
Assume that, ModelA has scheduling resource for InstA and ModelB has scheduling resource for InstB. This is what the llvm::MCSchedClassDesc looks like:

llvm::MCSchedClassDesc ModelASchedClasses[] = {
...
InstA, 0, ...
InstB, -1,...
};

llvm::MCSchedClassDesc ModelBSchedClasses[] = {
...
InstA, -1,...
InstB, 0,...
};
The -1 means invalid num of macro ops, while it is valid if it is >=0. This is what we look like now:

llvm::MCSchedClassDesc ModelASchedClasses[] = {
...
InstA, 0, ...
InstB, 0,...
};

llvm::MCSchedClassDesc ModelBSchedClasses[] = {
...
InstA, 0,...
InstB, 0,...
};
And compiler hit the assertion here because the SCDesc is valid now for both InstA and InstB.

Differential Revision: https://reviews.llvm.org/D67950

llvm-svn: 374524
2019-10-11 08:36:54 +00:00
..
aliasing.ll [ARM][ParallelDSP] Change the search for smlads 2019-07-11 07:47:50 +00:00
blocks.ll [ARM][ParallelDSP] Fix for sext input 2019-09-09 08:39:14 +00:00
complex_dot_prod.ll [ARM] Cortex-M4 schedule additions 2019-09-29 08:38:48 +00:00
exchange.ll [ARM][ParallelDSP] SExt mul for accumulation 2019-09-04 08:41:34 +00:00
inner-full-unroll.ll [ARM][ParallelDSP] Change the search for smlads 2019-07-11 07:47:50 +00:00
multi-use-loads.ll [ARM] Cortex-M4 schedule additions 2019-09-29 08:38:48 +00:00
overlapping.ll [ARM][ParallelDSP] SExt mul for accumulation 2019-09-04 08:41:34 +00:00
pr42729.ll [ARM][ParallelDSP] Change search for muls 2019-08-28 08:51:13 +00:00
pr43073.ll [ARM][ParallelDSP] SExt mul for accumulation 2019-09-04 08:41:34 +00:00
sext-acc.ll [ARM][ParallelDSP] Fix for sext input 2019-09-09 08:39:14 +00:00
smlad0.ll [ARM][ParallelDSP] Relax alias checks 2019-05-13 09:23:32 +00:00
smlad1.ll [ARM][ParallelDSP] Relax alias checks 2019-05-13 09:23:32 +00:00
smlad2.ll
smlad3.ll
smlad4.ll
smlad5.ll
smlad8.ll
smlad9.ll
smlad10.ll
smlad11.ll [ARM][ParallelDSP] Change search for muls 2019-08-28 08:51:13 +00:00
smlad12.ll [ARM][ParallelDSP] Change search for muls 2019-08-28 08:51:13 +00:00
smladx-1.ll [ARM][ParallelDSP] Relax alias checks 2019-05-13 09:23:32 +00:00
smlald0.ll [ARM][ParallelDSP] Relax alias checks 2019-05-13 09:23:32 +00:00
smlald1.ll [ARM][ParallelDSP] Relax alias checks 2019-05-13 09:23:32 +00:00
smlald2.ll [ARM][ParallelDSP] Relax alias checks 2019-05-13 09:23:32 +00:00
smlaldx-1.ll [ARM][ParallelDSP] Relax alias checks 2019-05-13 09:23:32 +00:00
smlaldx-2.ll [ARM][ParallelDSP] Change search for muls 2019-08-28 08:51:13 +00:00
unroll-n-jam-smlad.ll [TableGen] Fix a bug that MCSchedClassDesc is interfered between different SchedModel 2019-10-11 08:36:54 +00:00