llvm-project/llvm/lib/CodeGen
David Blaikie f2f898a044 DebugInfo: Omit an empty CU when a subprogram was moved into its use
When the only use of a CU is for a subprogram that's only emitted into
the using CU (to avoid cross-CU references in DWO files), avoid creating
that CU at all.

llvm-svn: 304111
2017-05-28 22:51:37 +00:00
..
AsmPrinter DebugInfo: Omit an empty CU when a subprogram was moved into its use 2017-05-28 22:51:37 +00:00
GlobalISel [GlobalISel] Add a localizer pass for target to use 2017-05-27 01:34:00 +00:00
MIRParser MIParser/MIRPrinter: Compute block successors if not explicitely specified 2017-05-05 21:09:30 +00:00
SelectionDAG [DAGCombiner] use narrow load to avoid vector extract 2017-05-27 14:07:03 +00:00
AggressiveAntiDepBreaker.cpp BitVector: add iterators for set bits 2017-05-17 01:07:53 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp Move llvm::canBeOmittedFromSymbolTable() to Analysis. 2017-03-31 04:46:31 +00:00
AntiDepBreaker.h Resubmit r301309: [DebugInfo][X86] Fix handling of DBG_VALUE's in post-RA scheduler. 2017-04-25 15:39:57 +00:00
AtomicExpandPass.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
BasicTargetTransformInfo.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
BranchCoalescing.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
BranchFolding.cpp LivePhysRegs: Skip reserved regs in computeLiveIns; NFCI 2017-05-26 06:32:31 +00:00
BranchFolding.h LivePhysRegs: Skip reserved regs in computeLiveIns; NFCI 2017-05-26 06:32:31 +00:00
BranchRelaxation.cpp BranchRelaxation: computeLiveIns() after creating new block 2017-05-27 00:53:48 +00:00
BuiltinGCs.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-02-27 22:45:06 +00:00
CMakeLists.txt Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB." 2017-05-18 18:50:05 +00:00
CalcSpillWeights.cpp
CallingConvLower.cpp [CodeGen] Remove dead call-or-prologue enum from CCState 2017-02-02 21:58:22 +00:00
CodeGen.cpp Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB." 2017-05-18 18:50:05 +00:00
CodeGenPrepare.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
CountingFunctionInserter.cpp Module::getOrInsertFunction is using C-style vararg instead of variadic templates. 2017-04-11 15:01:18 +00:00
CriticalAntiDepBreaker.cpp Resubmit r301309: [DebugInfo][X86] Fix handling of DBG_VALUE's in post-RA scheduler. 2017-04-25 15:39:57 +00:00
CriticalAntiDepBreaker.h
DFAPacketizer.cpp Remove unnecessary conditions as suggested by clang-tidy. NFC 2017-05-01 16:18:42 +00:00
DeadMachineInstructionElim.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
DetectDeadLanes.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
DwarfEHPrepare.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
EarlyIfConversion.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
EdgeBundles.cpp
ExecutionDepsFix.cpp [ExecutionDepsFix] Don't recurse over the CFG 2017-04-05 17:42:56 +00:00
ExpandISelPseudos.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
ExpandPostRAPseudos.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
ExpandReductions.cpp Add a late IR expansion pass for the experimental reduction intrinsics. 2017-05-10 09:42:49 +00:00
FEntryInserter.cpp [X86] Implement -mfentry 2017-01-31 17:00:27 +00:00
FaultMaps.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-02-27 22:45:06 +00:00
FuncletLayout.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
GCMetadata.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
GCMetadataPrinter.cpp
GCRootLowering.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
GCStrategy.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-02-27 22:45:06 +00:00
GlobalMerge.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
IfConversion.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
ImplicitNullChecks.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
InlineSpiller.cpp PR32382: Fix emitting complex DWARF expressions. 2017-04-18 01:21:53 +00:00
InterferenceCache.cpp
InterferenceCache.h
InterleavedAccessPass.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
IntrinsicLowering.cpp Module::getOrInsertFunction is using C-style vararg instead of variadic templates. 2017-04-11 15:01:18 +00:00
LLVMBuild.txt LLVMCodeGen: Add ProfileData into deps corresponding to r300277. 2017-04-14 00:36:06 +00:00
LLVMTargetMachine.cpp [LegacyPassManager] Remove TargetMachine constructors 2017-05-18 17:21:13 +00:00
LatencyPriorityQueue.cpp
LazyMachineBlockFrequencyInfo.cpp [LazyMachineBFI] Reimplement with getAnalysisIfAvailable 2017-02-23 17:30:01 +00:00
LexicalScopes.cpp Don't generate line&scope debug info for meta-instructions. 2017-05-22 20:47:09 +00:00
LiveDebugValues.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
LiveDebugVariables.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
LiveDebugVariables.h
LiveInterval.cpp RegisterCoalescer: Simplify subrange splitting code; NFC 2017-03-03 19:05:34 +00:00
LiveIntervalAnalysis.cpp [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-05-24 23:10:29 +00:00
LiveIntervalUnion.cpp LIU:::Query: Query LiveRange instead of LiveInterval; NFC 2017-03-01 21:48:12 +00:00
LivePhysRegs.cpp LivePhysRegs: Add default for removeRegsInMask(Clobbers); NFC 2017-05-26 21:50:51 +00:00
LiveRangeCalc.cpp RegisterCoalescer: Simplify subrange splitting code; NFC 2017-03-03 19:05:34 +00:00
LiveRangeCalc.h Extract LaneBitmask into a separate type 2016-12-15 14:36:06 +00:00
LiveRangeEdit.cpp [LiveRangeEdit] Don't mess up with LiveInterval when a new vreg is created. 2017-02-02 20:44:36 +00:00
LiveRangeUtils.h
LiveRegMatrix.cpp LiveRegMatrix: Fix some subreg interference checks 2017-03-02 00:35:08 +00:00
LiveRegUnits.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-02-17 21:43:25 +00:00
LiveStackAnalysis.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
LiveVariables.cpp [LiveVariables] Switch Kill/Defs sets to be DenseSet(s). 2017-05-11 19:37:43 +00:00
LocalStackSlotAllocation.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
LowLevelType.cpp [GlobalISel] Support vector-of-pointers in LLT 2017-04-19 07:23:57 +00:00
LowerEmuTLS.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MIRPrinter.cpp This reverts r302984 2017-05-13 10:59:05 +00:00
MIRPrintingPass.cpp MIParser/MIRPrinter: Compute block successors if not explicitely specified 2017-05-05 21:09:30 +00:00
MachineBasicBlock.cpp Refactor code to create getFallThrough method in MachineBasicBlock. 2017-03-31 15:55:37 +00:00
MachineBlockFrequencyInfo.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MachineBlockPlacement.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MachineBranchProbabilityInfo.cpp
MachineCSE.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MachineCombiner.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MachineCopyPropagation.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MachineDominanceFrontier.cpp
MachineDominators.cpp Do not verify MachimeDominatorTree if it is not calculated 2017-03-02 12:00:10 +00:00
MachineFrameInfo.cpp ARM: Compute MaxCallFrame size early 2017-05-05 22:04:05 +00:00
MachineFunction.cpp MachineFrameInfo: Move implementation to an own file; NFC 2017-04-26 23:36:58 +00:00
MachineFunctionPass.cpp Reverted: Track validity of pass results 2017-01-15 10:23:18 +00:00
MachineFunctionPrinterPass.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
MachineInstr.cpp Cleanup: Use DIExpression::prepend in buildDbgValueForSpill(). (NFC) 2017-04-28 18:30:36 +00:00
MachineInstrBundle.cpp CodeGen/Passes: Pass MachineFunction as functor arg; NFC 2016-10-24 23:23:02 +00:00
MachineLICM.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MachineLoopInfo.cpp New OptimizationRemarkEmitter pass for MIR 2017-01-25 23:20:33 +00:00
MachineModuleInfo.cpp [LegacyPassManager] Remove TargetMachine constructors 2017-05-18 17:21:13 +00:00
MachineModuleInfoImpls.cpp [WebAssembly] Add support for using a wasm global for the stack pointer. 2017-02-24 23:46:05 +00:00
MachineOptimizationRemarkEmitter.cpp [CodeGen] Teach opt remarks how to print MI instructions. 2017-02-23 21:05:33 +00:00
MachineOutliner.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MachinePassRegistry.cpp
MachinePipeliner.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MachinePostDominators.cpp
MachineRegionInfo.cpp Add MachineRegionInfoPassID to Passes.h. 2017-04-11 11:40:55 +00:00
MachineRegisterInfo.cpp [MIR] Support Customed Register Mask and CSRs 2017-03-19 08:14:18 +00:00
MachineSSAUpdater.cpp Retire llvm::alignOf in favor of C++11 alignof. 2016-10-20 15:02:18 +00:00
MachineScheduler.cpp ScheduleDAGInstrs: Fix fixupKills() 2017-05-27 02:50:50 +00:00
MachineSink.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MachineTraceMetrics.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
MachineVerifier.cpp MachineVerifier: Remove unused set; NFC 2017-05-26 21:50:48 +00:00
OptimizePHIs.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
PHIElimination.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
PHIEliminationUtils.cpp Place the lowered phi instruction(s) before the DEBUG_VALUE entry 2016-09-16 14:07:29 +00:00
PHIEliminationUtils.h
ParallelCG.cpp Bitcode: Change module reader functions to return an llvm::Expected. 2016-11-13 07:00:17 +00:00
PatchableFunction.cpp [CodeGen] Rename MachineInstrBuilder::addOperand. NFC 2017-01-13 09:58:52 +00:00
PeepholeOptimizer.cpp PeepholeOptimizer: Do not replace SubregToReg(bitcast like) 2017-01-09 21:38:17 +00:00
PostRAHazardRecognizer.cpp
PostRASchedulerList.cpp ScheduleDAGInstrs: Fix fixupKills() 2017-05-27 02:50:50 +00:00
PreISelIntrinsicLowering.cpp
ProcessImplicitDefs.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
PrologEpilogInserter.cpp AArch64/PEI: Do not add reserved regs to liveins 2017-05-27 03:38:02 +00:00
PseudoSourceValue.cpp Fix crashing on TargetCustom PseudoSourceValues 2017-03-28 20:33:12 +00:00
README.txt
RegAllocBase.cpp Timer: Track name and description. 2016-11-18 19:43:18 +00:00
RegAllocBase.h Timer: Track name and description. 2016-11-18 19:43:18 +00:00
RegAllocBasic.cpp LIU::Query: Remove always false member+getter; NFC 2017-03-01 21:02:52 +00:00
RegAllocFast.cpp Move size and alignment information of regclass to TargetRegisterInfo 2017-04-24 18:55:33 +00:00
RegAllocGreedy.cpp BitVector: add iterators for set bits 2017-05-17 01:07:53 +00:00
RegAllocPBQP.cpp Disable Callee Saved Registers 2017-03-14 09:09:26 +00:00
RegUsageInfoCollector.cpp [IPRA] Change algorithm for RegUsageInfoCollector. 2017-03-13 21:42:53 +00:00
RegUsageInfoPropagate.cpp Use StringRef in Pass/PassManager APIs (NFC) 2016-10-01 02:56:57 +00:00
RegisterClassInfo.cpp Disable Callee Saved Registers 2017-03-14 09:09:26 +00:00
RegisterCoalescer.cpp LiveIntervalAnalysis: Fix missing case in pruneSubRegValues() 2017-05-19 00:18:03 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Revert "Correct register pressure calculation in presence of subregs" 2017-02-24 21:56:16 +00:00
RegisterScavenging.cpp [RegScavenger] Rangify a loop, NFC 2017-05-09 17:16:52 +00:00
RegisterUsageInfo.cpp
RenameIndependentSubregs.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
ResetMachineFunctionPass.cpp GlobalISel: Abort in ResetMachineFunctionPass if fallback isn't enabled 2017-01-13 23:46:11 +00:00
SafeStack.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
SafeStackColoring.cpp [safestack] Disable stack coloring by default. 2017-05-19 20:58:48 +00:00
SafeStackColoring.h
SafeStackLayout.cpp
SafeStackLayout.h
ScalarizeMaskedMemIntrin.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
ScheduleDAG.cpp MachineScheduler/ScheduleDAG: Add support for GetSubGraph 2017-03-28 05:12:31 +00:00
ScheduleDAGInstrs.cpp ScheduleDAGInstrs: Fix fixupKills() 2017-05-27 02:50:50 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC). 2017-02-22 22:32:51 +00:00
ShadowStackGCLowering.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
ShrinkWrap.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
SjLjEHPrepare.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
SlotIndexes.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
SpillPlacement.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
SpillPlacement.h
Spiller.h
SplitKit.cpp SplitKit: Fix subreg copy related problems 2017-03-21 21:58:08 +00:00
SplitKit.h SplitKit: Correctly implement partial subregister copies 2017-03-17 00:41:39 +00:00
StackColoring.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
StackMapLivenessAnalysis.cpp LivePhysReg: Use reference instead of pointer in init(); NFC 2016-12-08 00:15:51 +00:00
StackMaps.cpp [StackMaps] Increase the size of the "location size" field 2017-04-28 04:48:42 +00:00
StackProtector.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
StackSlotColoring.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
TailDuplication.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
TailDuplicator.cpp [CodeGen] Fix uninitialized variables exposed by r303084 2017-05-22 21:33:54 +00:00
TargetFrameLoweringImpl.cpp Disable Callee Saved Registers 2017-03-14 09:09:26 +00:00
TargetInstrInfo.cpp Move size and alignment information of regclass to TargetRegisterInfo 2017-04-24 18:55:33 +00:00
TargetLoweringBase.cpp BitVector: add iterators for set bits 2017-05-17 01:07:53 +00:00
TargetLoweringObjectFileImpl.cpp Ignore !associated metadata with null argument. 2017-05-08 23:46:20 +00:00
TargetOptionsImpl.cpp Remove LessPreciseFPMADOption from TargetOptions along with all of the 2017-03-17 00:38:03 +00:00
TargetPassConfig.cpp [LegacyPassManager] Remove TargetMachine constructors 2017-05-18 17:21:13 +00:00
TargetRegisterInfo.cpp BitVector: add iterators for set bits 2017-05-17 01:07:53 +00:00
TargetSchedule.cpp This patch closes PR#32216: Better testing of schedule model instruction latencies/throughputs. 2017-04-14 07:44:23 +00:00
TargetSubtargetInfo.cpp This patch closes PR#32216: Better testing of schedule model instruction latencies/throughputs. 2017-04-14 07:44:23 +00:00
TwoAddressInstructionPass.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
UnreachableBlockElim.cpp [UnreachableBlockElim] Check return value of constrainRegClass(). 2017-05-10 06:33:43 +00:00
VirtRegMap.cpp Move size and alignment information of regclass to TargetRegisterInfo 2017-04-24 18:55:33 +00:00
WinEHPrepare.cpp CodeGen: Rename DEBUG_TYPE to match passnames 2017-05-25 21:26:32 +00:00
XRayInstrumentation.cpp [XRay] Detect loops in functions being lowered 2017-05-04 01:24:26 +00:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.