forked from OSchip/llvm-project
115 lines
4.5 KiB
ArmAsm
115 lines
4.5 KiB
ArmAsm
// REQUIRES: arm
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// RUN: llvm-mc -filetype=obj -triple=thumbv7a-none-linux-gnueabi %p/Inputs/arm-plt-reloc.s -o %t1
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// RUN: llvm-mc -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t2
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// RUN: ld.lld %t1 %t2 -o %t
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// RUN: llvm-objdump --triple=thumbv7a-none-linux-gnueabi -d %t | FileCheck %s
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// RUN: ld.lld -shared %t1 %t2 -o %t.so
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// RUN: llvm-objdump --triple=thumbv7a-none-linux-gnueabi -d %t.so | FileCheck --check-prefix=DSO %s
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// RUN: llvm-readobj -S -r %t.so | FileCheck -check-prefix=DSOREL %s
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//
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// Test PLT entry generation
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.syntax unified
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.text
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.align 2
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.globl _start
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.type _start,%function
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_start:
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// FIXME, interworking is only supported for BL via BLX at the moment, when
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// interworking thunks are available for b.w and b<cond>.w this can be altered
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// to test the different forms of interworking.
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bl func1
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bl func2
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bl func3
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// Executable, expect no PLT
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// CHECK: Disassembly of section .text:
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// CHECK-EMPTY:
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// CHECK-NEXT: <func1>:
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// CHECK-NEXT: 200b4: 70 47 bx lr
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// CHECK: <func2>:
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// CHECK-NEXT: 200b6: 70 47 bx lr
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// CHECK: <func3>:
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// CHECK-NEXT: 200b8: 70 47 bx lr
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// CHECK-NEXT: 200ba: d4 d4
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// CHECK: <_start>:
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// . + 4 -12 = 0x200b4 = func1
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// CHECK-NEXT: 200bc: ff f7 fa ff bl #-12
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// . + 4 -14 = 0x200b6 = func2
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// CHECK-NEXT: 200c0: ff f7 f9 ff bl #-14
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// . + 4 -16 = 0x200b8 = func3
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// CHECK-NEXT: 200c4: ff f7 f8 ff bl #-16
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// Expect PLT entries as symbols can be preempted
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// .text is Thumb and .plt is ARM, llvm-objdump can currently only disassemble
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// as ARM or Thumb. Work around by disassembling twice.
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// DSO: Disassembly of section .text:
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// DSO-EMPTY:
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// DSO-NEXT: <func1>:
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// DSO-NEXT: 10214: 70 47 bx lr
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// DSO: <func2>:
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// DSO-NEXT: 10216: 70 47 bx lr
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// DSO: <func3>:
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// DSO-NEXT: 10218: 70 47 bx lr
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// DSO-NEXT: 1021a: d4 d4 bmi #-88
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// DSO: <_start>:
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// . + 48 + 4 = 0x10250 = PLT func1
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// DSO-NEXT: 1021c: 00 f0 18 e8 blx #48
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// . + 60 + 4 = 0x10260 = PLT func2
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// DSO-NEXT: 10220: 00 f0 1e e8 blx #60
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// . + 72 + 4 = 0x10270 = PLT func3
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// DSO-NEXT: 10224: 00 f0 24 e8 blx #72
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// DSO: Disassembly of section .plt:
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// DSO-EMPTY:
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// DSO-NEXT: <$a>:
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// DSO-NEXT: 10230: 04 e0 2d e5 str lr, [sp, #-4]!
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// (0x10234 + 8) + (0 RoR 12) + 8192 + 164 = 0x32e0 = .got.plt[3]
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// DSO-NEXT: 10234: 00 e6 8f e2 add lr, pc, #0, #12
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// DSO-NEXT: 10238: 20 ea 8e e2 add lr, lr, #32
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// DSO-NEXT: 1023c: a4 f0 be e5 ldr pc, [lr, #164]!
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// DSO: <$d>:
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// DSO-NEXT: 10240: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSO-NEXT: 10244: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSO-NEXT: 10248: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSO-NEXT: 1024c: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSO: <$a>:
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// (0x10250 + 8) + (0 RoR 12) + 8192 + 140 = 0x32e4
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// DSO-NEXT: 10250: 00 c6 8f e2 add r12, pc, #0, #12
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// DSO-NEXT: 10254: 20 ca 8c e2 add r12, r12, #32
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// DSO-NEXT: 10258: 8c f0 bc e5 ldr pc, [r12, #140]!
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// DSO: <$d>:
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// DSO-NEXT: 1025c: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSO: <$a>:
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// (0x10260 + 8) + (0 RoR 12) + 8192 + 128 = 0x32e8
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// DSO-NEXT: 10260: 00 c6 8f e2 add r12, pc, #0, #12
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// DSO-NEXT: 10264: 20 ca 8c e2 add r12, r12, #32
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// DSO-NEXT: 10268: 80 f0 bc e5 ldr pc, [r12, #128]!
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// DSO: <$d>:
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// DSO-NEXT: 1026c: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSO: <$a>:
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// (0x10270 + 8) + (0 RoR 12) + 8192 + 116 = 0x32ec
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// DSO-NEXT: 10270: 00 c6 8f e2 add r12, pc, #0, #12
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// DSO-NEXT: 10274: 20 ca 8c e2 add r12, r12, #32
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// DSO-NEXT: 10278: 74 f0 bc e5 ldr pc, [r12, #116]!
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// DSO: <$d>:
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// DSO-NEXT: 1027c: d4 d4 d4 d4 .word 0xd4d4d4d4
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// DSOREL: Name: .got.plt
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// DSOREL-NEXT: Type: SHT_PROGBITS
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// DSOREL-NEXT: Flags [
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// DSOREL-NEXT: SHF_ALLOC
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// DSOREL-NEXT: SHF_WRITE
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// DSOREL-NEXT: ]
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// DSOREL-NEXT: Address: 0x302D8
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// DSOREL-NEXT: Offset:
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// DSOREL-NEXT: Size: 24
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// DSOREL-NEXT: Link:
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// DSOREL-NEXT: Info:
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// DSOREL-NEXT: AddressAlignment: 4
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// DSOREL-NEXT: EntrySize:
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// DSOREL: Relocations [
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// DSOREL-NEXT: Section (5) .rel.plt {
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// DSOREL-NEXT: 0x302E4 R_ARM_JUMP_SLOT func1
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// DSOREL-NEXT: 0x302E8 R_ARM_JUMP_SLOT func2
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// DSOREL-NEXT: 0x302EC R_ARM_JUMP_SLOT func3
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