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llvm-project/llvm/test/MC/Disassembler/ARM
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Simi Pallipurath 75c6bfeac9 [ARM]Decoding MSR with unpredictable destination register causes an assert 
This patch handling:

    Enable parsing of raw encodings of system registers .
    Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
    Disassemble msr/mrs with unpredictable sysregs as SoftFail.
    Fix regression due to SoftFailing some encodings.

Patch by Chris Ryder

Differential revision:https://reviews.llvm.org/D43374

llvm-svn: 326803
 		2018-03-06 15:21:19 +00:00
..
addrmode2-reencoding.txt
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arm-LDREXD-reencoding.txt
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arm-STREXD-reencoding.txt
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arm-tests.txt
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arm-thumb-trustzone.txt
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arm-trustzone.txt
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arm-vmrs_vmsr.txt [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode 2017-10-18 14:47:37 +00:00
armv8.1a.txt
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armv8.2a-dotprod-a32.s [ARM] Assembler support for the ARMv8.2a dot product instructions 2017-08-11 09:52:30 +00:00
armv8.2a-dotprod-t32.s [ARM] Assembler support for the ARMv8.2a dot product instructions 2017-08-11 09:52:30 +00:00
armv8.3a-js-arm.txt [ARM][AArch64] v8.3-A Javascript Conversion 2017-08-22 11:08:21 +00:00
armv8.3a-js-thumb.txt [ARM][AArch64] v8.3-A Javascript Conversion 2017-08-22 11:08:21 +00:00
basic-arm-instructions-v8.txt
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basic-arm-instructions.txt
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crc32-thumb.txt
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crc32.txt
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csdb-arm.txt [ARM][AArch64] Add CSDB speculation barrier instruction 2018-02-06 09:24:47 +00:00
csdb-thumb.txt [ARM][AArch64] Add CSDB speculation barrier instruction 2018-02-06 09:24:47 +00:00
d16.txt
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dfb-arm.txt [ARM] Armv8-R DFB instruction 2017-12-21 11:17:49 +00:00
dfb-thumb.txt [ARM] Armv8-R DFB instruction 2017-12-21 11:17:49 +00:00
fp-armv8.txt
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fp-encoding.txt Revert "[ARM] Fix assembly and disassembly for VMRS/VMSR" 2017-08-08 17:16:46 +00:00
fullfp16-arm-neg.txt [ARM] Add ARMv8.2-A FP16 scalar instructions 2016-01-25 10:26:26 +00:00
fullfp16-arm.txt [ARM] Add ARMv8.2-A FP16 scalar instructions 2016-01-25 10:26:26 +00:00
fullfp16-neon-arm-neg.txt [ARM] Add ARMv8.2-A FP16 vector instructions 2015-12-16 12:37:39 +00:00
fullfp16-neon-arm.txt [ARM] Add ARMv8.2-A FP16 vector instructions 2015-12-16 12:37:39 +00:00
fullfp16-neon-thumb-neg.txt [ARM] Add ARMv8.2-A FP16 vector instructions 2015-12-16 12:37:39 +00:00
fullfp16-neon-thumb.txt [ARM] Add ARMv8.2-A FP16 vector instructions 2015-12-16 12:37:39 +00:00
fullfp16-thumb-neg.txt [ARM] Add ARMv8.2-A FP16 scalar instructions 2016-01-25 10:26:26 +00:00
fullfp16-thumb.txt [ARM] Add ARMv8.2-A FP16 scalar instructions 2016-01-25 10:26:26 +00:00
hex-immediates.txt
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invalid-FSTMX-arm.txt
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invalid-IT-CC15.txt
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invalid-armv7.txt [ARM] Re-commit r324600 with fixed LLVMBuild.txt 2018-02-08 14:31:22 +00:00
invalid-armv8.1a.txt
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invalid-armv8.txt
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invalid-because-armv7.txt
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invalid-thumb-MSR-MClass.txt [ARM]Decoding MSR with unpredictable destination register causes an assert 2018-03-06 15:21:19 +00:00
invalid-thumbv7-xfail.txt
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invalid-thumbv7.txt [ARM] Re-commit r324600 with fixed LLVMBuild.txt 2018-02-08 14:31:22 +00:00
invalid-thumbv8.1a.txt
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invalid-thumbv8.txt
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invalid-virtexts.arm.txt
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ldrd-armv4.txt
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lit.local.cfg
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load-store-acquire-release-v8-thumb.txt
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load-store-acquire-release-v8.txt
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marked-up-thumb.txt
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memory-arm-instructions.txt
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move-banked-regs-arm.txt
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move-banked-regs-thumb.txt
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neon-complex-arm.txt [ARM] v8.3-a complex number support 2017-09-29 13:11:33 +00:00
neon-complex-thumb.txt [ARM] v8.3-a complex number support 2017-09-29 13:11:33 +00:00
neon-crypto.txt
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neon-tests.txt
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neon-v8.txt
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neon.txt
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neont-VLD-reencoding.txt
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neont-VST-reencoding.txt
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neont2.txt
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ras-extension-arm.txt RAS extensions are part of ARMv8.2-A. This change enables them by introducing a 2016-06-03 14:03:27 +00:00
ras-extension-thumb.txt RAS extensions are part of ARMv8.2-A. This change enables them by introducing a 2016-06-03 14:03:27 +00:00
thumb-MSR-MClass.txt
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thumb-fp-armv8.txt
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thumb-neon-crypto.txt
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thumb-neon-v8.txt
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thumb-printf.txt
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thumb-tests.txt
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thumb-v8.1a.txt
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thumb-v8.txt
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thumb-vmrs_vmsr.txt [ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode 2017-10-18 14:47:37 +00:00
thumb1.txt
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thumb2-preloads.txt
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thumb2-v8.txt
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thumb2-v8m.txt [ARM] Add new system registers to ARMv8-M Baseline/Mainline 2016-01-25 11:25:36 +00:00
thumb2.txt
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unpredictable-ADC-arm.txt
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unpredictable-ADDREXT3-arm.txt
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unpredictable-AExtI-arm.txt
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unpredictable-AI1cmp-arm.txt
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unpredictable-BFI.txt
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unpredictable-LDR-arm.txt
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unpredictable-LDRD-arm.txt
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unpredictable-LSL-regform.txt
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unpredictable-MRRC2-arm.txt
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unpredictable-MRS-arm.txt
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unpredictable-MUL-arm.txt
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unpredictable-MVN-arm.txt [ARM] Add support for unpredictable MVN instructions. 2018-02-01 12:06:57 +00:00
unpredictable-RSC-arm.txt
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unpredictable-SEL-arm.txt
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unpredictable-SHADD16-arm.txt
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unpredictable-SSAT-arm.txt [ARM] Saturation instructions are DSP-only 2016-07-25 22:25:25 +00:00
unpredictable-STRBrs-arm.txt
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unpredictable-UQADD8-arm.txt
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unpredictable-swp-arm.txt
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unpredictables-thumb.txt
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vfp4.txt
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virtexts-arm.txt
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virtexts-thumb.txt
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