forked from OSchip/llvm-project
122 lines
3.8 KiB
LLVM
122 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s --check-prefixes=CHECK
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; RUN: FileCheck --check-prefix=WARN --allow-empty %s < %t
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; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
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; WARN-NOT: warning
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; LEGAL INTEGER TYPES
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define <vscale x 2 x i64> @stepvector_nxv2i64() {
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; CHECK-LABEL: stepvector_nxv2i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: index z0.d, #0, #1
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
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ret <vscale x 2 x i64> %0
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}
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define <vscale x 4 x i32> @stepvector_nxv4i32() {
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; CHECK-LABEL: stepvector_nxv4i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: index z0.s, #0, #1
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
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ret <vscale x 4 x i32> %0
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}
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define <vscale x 8 x i16> @stepvector_nxv8i16() {
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; CHECK-LABEL: stepvector_nxv8i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: index z0.h, #0, #1
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
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ret <vscale x 8 x i16> %0
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}
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define <vscale x 16 x i8> @stepvector_nxv16i8() {
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; CHECK-LABEL: stepvector_nxv16i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: index z0.b, #0, #1
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
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ret <vscale x 16 x i8> %0
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}
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; ILLEGAL INTEGER TYPES
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define <vscale x 4 x i64> @stepvector_nxv4i64() {
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; CHECK-LABEL: stepvector_nxv4i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cntd x8
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; CHECK-NEXT: mov z1.d, x8
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; CHECK-NEXT: index z0.d, #0, #1
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; CHECK-NEXT: add z1.d, z0.d, z1.d
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
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ret <vscale x 4 x i64> %0
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}
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define <vscale x 16 x i32> @stepvector_nxv16i32() {
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; CHECK-LABEL: stepvector_nxv16i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cntw x9
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; CHECK-NEXT: cnth x8
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; CHECK-NEXT: index z0.s, #0, #1
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; CHECK-NEXT: mov z1.s, w9
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; CHECK-NEXT: mov z3.s, w8
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; CHECK-NEXT: add z1.s, z0.s, z1.s
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; CHECK-NEXT: add z2.s, z0.s, z3.s
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; CHECK-NEXT: add z3.s, z1.s, z3.s
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
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ret <vscale x 16 x i32> %0
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}
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define <vscale x 2 x i32> @stepvector_nxv2i32() {
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; CHECK-LABEL: stepvector_nxv2i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: index z0.d, #0, #1
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
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ret <vscale x 2 x i32> %0
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}
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define <vscale x 4 x i16> @stepvector_nxv4i16() {
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; CHECK-LABEL: stepvector_nxv4i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: index z0.s, #0, #1
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
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ret <vscale x 4 x i16> %0
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}
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define <vscale x 8 x i8> @stepvector_nxv8i8() {
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; CHECK-LABEL: stepvector_nxv8i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: index z0.h, #0, #1
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
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ret <vscale x 8 x i8> %0
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}
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declare <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
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declare <vscale x 4 x i32> @llvm.experimental.stepvector.nxv4i32()
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declare <vscale x 8 x i16> @llvm.experimental.stepvector.nxv8i16()
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declare <vscale x 16 x i8> @llvm.experimental.stepvector.nxv16i8()
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declare <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
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declare <vscale x 16 x i32> @llvm.experimental.stepvector.nxv16i32()
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declare <vscale x 2 x i32> @llvm.experimental.stepvector.nxv2i32()
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declare <vscale x 8 x i8> @llvm.experimental.stepvector.nxv8i8()
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declare <vscale x 4 x i16> @llvm.experimental.stepvector.nxv4i16()
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