forked from OSchip/llvm-project
47 lines
1.1 KiB
Plaintext
47 lines
1.1 KiB
Plaintext
{
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"arrays" : [
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{
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"name" : "MemRef_A",
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"sizes" : [ "*" ],
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"type" : "i64"
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},
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{
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"name" : "MemRef_B",
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"sizes" : [ "*" ],
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"type" : "float"
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},
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{
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"name" : "MemRef_C",
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"sizes" : [ "*" ],
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"type" : "float"
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}
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],
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"context" : "{ : }",
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"name" : "%bb1---%bb12",
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"statements" : [
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{
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"accesses" : [
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb2__TO__bb9[i0] -> MemRef_A[i0] }"
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},
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{
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"kind" : "read",
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"relation" : "{ Stmt_bb2__TO__bb9[i0] -> MemRef_B[i0] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_bb2__TO__bb9[i0] -> MemRef_B[i0] }"
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},
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{
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"kind" : "write",
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"relation" : "{ Stmt_bb2__TO__bb9[i0] -> MemRef_C[0] }"
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}
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],
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"domain" : "{ Stmt_bb2__TO__bb9[i0] : 0 <= i0 <= 1023 }",
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"name" : "Stmt_bb2__TO__bb9",
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"schedule" : "{ Stmt_bb2__TO__bb9[i0] -> [i0] }"
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}
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]
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}
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