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AsmParser
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[MC] Change EndOfStatement "unexpected tokens in .xxx directive " to "expected newline"
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2022-06-05 15:11:01 -07:00 |
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Disassembler
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Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`
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2022-05-15 08:44:58 +08:00 |
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MCTargetDesc
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[NFC][Alignment] Use Align in MCAlignFragment
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2022-06-15 12:31:00 +00:00 |
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TargetInfo
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Fix shlib builds for all lib/Target/*/TargetInfo libs
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2021-10-08 15:21:13 -07:00 |
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CMakeLists.txt
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[RISCV] Add pre-emit pass to make more instructions compressible
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2022-05-25 09:25:02 +01:00 |
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RISCV.h
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[RISCV] Pass OptLevel to `RISCVDAGToDAGISel` correctly
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2022-05-30 17:22:50 -07:00 |
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RISCV.td
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[RISCV] Add a subtarget feature to enable unaligned scalar loads and stores
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2022-05-26 15:25:47 -07:00 |
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RISCVAsmPrinter.cpp
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[RISCV] Lower case the first letter of LowerRISCVMachineOperandToMCOperand. NFC
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2022-05-01 14:13:55 -07:00 |
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVExpandAtomicPseudoInsts.cpp
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[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
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2022-01-28 09:51:49 -08:00 |
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RISCVExpandPseudoInsts.cpp
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[RISCV] Fixing undefined physical register issue when subreg liveness tracking enabled.
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2022-06-15 16:23:39 +08:00 |
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RISCVFrameLowering.cpp
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[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.
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2022-06-12 10:47:21 -07:00 |
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RISCVFrameLowering.h
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[RISCV] Fix RVV stack frame alignment bugs
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2022-05-24 06:53:51 +01:00 |
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RISCVGatherScatterLowering.cpp
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[RISCV] Don't require loop simplify form in RISCVGatherScatterLowering.
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2022-06-10 13:00:20 -07:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Move creation of constant pools from isel to lowering.
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2022-06-13 09:07:57 -07:00 |
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RISCVISelDAGToDAG.h
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[RISCV] Reduce scalar load/store isel patterns to a single ComplexPattern. NFCI
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2022-06-03 09:00:17 -07:00 |
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RISCVISelLowering.cpp
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[RISCV] Disable matchSplatAsGather for i1 vectors to prevent creating illegal nodes.
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2022-06-13 13:41:39 -07:00 |
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RISCVISelLowering.h
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[RISCV] Move creation of constant pools from isel to lowering.
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2022-06-13 09:07:57 -07:00 |
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RISCVInsertVSETVLI.cpp
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[RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF.
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2022-06-15 13:58:40 +08:00 |
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RISCVInstrFormats.td
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[RISCV] Support mask policy for RVV IR intrinsics.
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2022-03-22 01:19:16 -07:00 |
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RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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[RISCV] Remove Zvamo Extention
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2021-12-20 10:28:39 +08:00 |
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RISCVInstrInfo.cpp
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[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.
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2022-06-12 10:47:21 -07:00 |
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RISCVInstrInfo.h
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[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.
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2022-06-12 10:47:21 -07:00 |
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RISCVInstrInfo.td
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[RISCV] Fix use of texternalsym in output pattern where input was tglobaladdr. NFC
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2022-06-13 15:42:42 -07:00 |
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RISCVInstrInfoA.td
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[RISCV] Reduce scalar load/store isel patterns to a single ComplexPattern. NFCI
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2022-06-03 09:00:17 -07:00 |
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RISCVInstrInfoC.td
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[llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets
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2021-11-18 11:14:27 +08:00 |
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RISCVInstrInfoD.td
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[RISCV] Add more patterns for FNMADD
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2022-06-04 12:31:45 +08:00 |
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RISCVInstrInfoF.td
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[RISCV] Add more patterns for FNMADD
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2022-06-04 12:31:45 +08:00 |
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RISCVInstrInfoM.td
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[RISCV] Add isCommutable to ADD/ADDW/MUL/AND/OR/XOR/MIN/MAX/CLMUL
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2022-04-25 10:53:41 -07:00 |
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RISCVInstrInfoV.td
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[RISCV][RVV] Add Uses = [FRM] and mayRaiseFPException = true to RVV instructions
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2022-03-31 01:33:17 -07:00 |
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RISCVInstrInfoVPseudos.td
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[RISCV][NFC] Set default value for BaseInstr in RISCVVPseudo
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2022-06-15 10:59:45 +08:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV] Replace uses of VLOpFrag in VLMax patterns with srcvalue.
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2022-06-14 19:19:35 -07:00 |
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RISCVInstrInfoVVLPatterns.td
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[RISCV] Fix vnsrl/vnsra isel patterns that are dropping VL.
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2022-05-24 21:38:59 -07:00 |
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RISCVInstrInfoZb.td
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[RISCV] Use isShiftedInt to improve readability. NFC
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2022-06-12 21:04:45 -07:00 |
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RISCVInstrInfoZfh.td
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[RISCV] Add more patterns for FNMADD
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2022-06-04 12:31:45 +08:00 |
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RISCVInstrInfoZk.td
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[RISCV] Adjust some comments.
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2022-02-01 22:53:54 +08:00 |
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RISCVInstructionSelector.cpp
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[Target] Remove redundant member initialization (NFC)
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2022-01-06 22:01:44 -08:00 |
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RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp
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[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.
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2022-06-12 10:47:21 -07:00 |
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RISCVMachineFunctionInfo.cpp
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llvm-reduce: Add cloning of target MachineFunctionInfo
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2022-06-07 10:14:48 -04:00 |
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RISCVMachineFunctionInfo.h
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llvm-reduce: Add cloning of target MachineFunctionInfo
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2022-06-07 10:14:48 -04:00 |
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RISCVMakeCompressible.cpp
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[RISCV] Add pre-emit pass to make more instructions compressible
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2022-05-25 09:25:02 +01:00 |
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RISCVMergeBaseOffset.cpp
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Recommit "[RISCV] Teach RISCVMergeBaseOffset about cases where we use SHXADD to add some immediates."
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2022-06-13 11:35:44 -07:00 |
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RISCVRedundantCopyElimination.cpp
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[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
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2022-02-04 10:43:46 -08:00 |
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RISCVRegisterBankInfo.cpp
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[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)
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2022-03-27 22:22:37 -07:00 |
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RISCVRegisterBankInfo.h
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[nfc][codegen] Move RegisterBank[Info].h under CodeGen
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2022-03-01 21:53:25 -08:00 |
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.
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2022-06-12 10:47:21 -07:00 |
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RISCVRegisterInfo.h
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[RISCV] Set CostPerUse to 1 iff RVC is enabled
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2022-01-21 14:44:26 +08:00 |
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RISCVRegisterInfo.td
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[RISCV] Add llvm.read.register support for vlenb
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2022-05-13 09:12:02 -07:00 |
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RISCVSExtWRemoval.cpp
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[RISCV] transform MI to W variant to remove sext.w
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2022-04-22 10:59:26 -07:00 |
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RISCVSchedRocket.td
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[RISCV] Add schedule class for Zbp extension and Zbr extension
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2022-03-01 07:35:59 +00:00 |
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RISCVSchedSiFive7.td
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[RISCV] Add schedule class for Zbp extension and Zbr extension
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2022-03-01 07:35:59 +00:00 |
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RISCVSchedule.td
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RISCVScheduleB.td
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[RISCV] Add schedule class for Zbp extension and Zbr extension
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2022-03-01 07:35:59 +00:00 |
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RISCVScheduleV.td
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RISCVSubtarget.cpp
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Revert "[RISCV] Enable subregister liveness tracking for RVV."
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2022-05-13 10:59:58 -07:00 |
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RISCVSubtarget.h
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[RISCV] Add a subtarget feature to enable unaligned scalar loads and stores
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2022-05-26 15:25:47 -07:00 |
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RISCVSystemOperands.td
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[RISCV] Initially support the K-extension instructions on the LLVM MC layer
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2022-01-24 14:45:35 +08:00 |
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RISCVTargetMachine.cpp
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[RISCV] Pass OptLevel to `RISCVDAGToDAGISel` correctly
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2022-05-30 17:22:50 -07:00 |
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RISCVTargetMachine.h
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[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file
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2022-04-08 11:55:48 +08:00 |
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
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[RISCV] Refine costs for i1 reductions
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2022-06-10 13:21:52 -07:00 |
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RISCVTargetTransformInfo.h
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[RISCV] Implement isElementTypeLegalForScalableVector TTI hook
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2022-06-10 13:20:58 -07:00 |
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