llvm-project/clang/test/CodeGen/aarch64-sve2-intrinsics
Sander de Smalen a5e0389b2a [AArch64] Define ACLE FP conversion intrinsics with more specific predicate.
This patch changes the FP conversion intrinsics to take a predicate
that matches the number of lanes for the vector with the widest element
type as opposed to using <vscale x 16 x i1>.

For example:
```<vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 8 x half>)```
now uses <vscale x 4 x i1> instead of <vscale x 16 x i1>

And similar for:
```<vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x double>)```
where the predicate now matches the wider type, so <vscale x 2 x i1>.

Reviewers: efriedma, SjoerdMeijer, paulwalker-arm, rengolin

Reviewed By: efriedma

Tags: #clang

Differential Revision: https://reviews.llvm.org/D78402
2020-04-23 10:53:23 +01:00
..
negative
acle_sve2_cvtlt.c [AArch64] Define ACLE FP conversion intrinsics with more specific predicate. 2020-04-23 10:53:23 +01:00
acle_sve2_cvtnt.c [AArch64] Define ACLE FP conversion intrinsics with more specific predicate. 2020-04-23 10:53:23 +01:00
acle_sve2_cvtx.c [AArch64] Define ACLE FP conversion intrinsics with more specific predicate. 2020-04-23 10:53:23 +01:00
acle_sve2_cvtxnt.c [AArch64] Define ACLE FP conversion intrinsics with more specific predicate. 2020-04-23 10:53:23 +01:00
acle_sve2_ldnt1.c
acle_sve2_ldnt1sb.c
acle_sve2_ldnt1sh.c
acle_sve2_ldnt1sw.c
acle_sve2_ldnt1ub.c
acle_sve2_ldnt1uh.c
acle_sve2_ldnt1uw.c
acle_sve2_qshlu.c
acle_sve2_shrnb.c
acle_sve2_stnt1.c
acle_sve2_stnt1b.c
acle_sve2_stnt1h.c
acle_sve2_stnt1w.c
acle_sve2_whilege.c [SveEmitter] Add builtins for svwhile 2020-04-22 21:47:47 +01:00
acle_sve2_whilegt.c [SveEmitter] Add builtins for svwhile 2020-04-22 21:47:47 +01:00
acle_sve2_whilerw.c [SveEmitter] Add builtins for svwhilerw/svwhilewr 2020-04-22 21:49:18 +01:00
acle_sve2_whilewr.c [SveEmitter] Add builtins for svwhilerw/svwhilewr 2020-04-22 21:49:18 +01:00