llvm-project/llvm/test/CodeGen
Sander de Smalen f13beac51b [AArch64][SVE] Preserve full vector regs over EH edge.
Unwinders may only preserve the lower 64bits of Neon and SVE registers,
as only the registers in the base ABI are guaranteed to be preserved
over the exception edge. The caller will need to preserve additional
registers for when the call throws an exception and the unwinder has
tried to recover state.

For  e.g.

    svint32_t bar(svint32_t);
    svint32_t foo(svint32_t x, bool *err) {
      try { bar(x); } catch (...) { *err = true; }
      return x;
    }

`z0` needs to be spilled before the call to `bar(x)` and reloaded before
returning from foo, as the exception handler may have clobbered z0.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D84737
2020-09-02 10:54:18 +01:00
..
AArch64 [AArch64][SVE] Preserve full vector regs over EH edge. 2020-09-02 10:54:18 +01:00
AMDGPU [MemCpyOptimizer] Preserve analyses and replace use of lambdas to get them. 2020-09-01 17:35:40 -07:00
ARC [ARC] Update brcc test. 2020-08-28 17:07:25 -07:00
ARM Revert "[ARM] Register pressure with -mthumb forces register reload before each call" 2020-09-01 07:39:54 +01:00
AVR
BPF BPF: add a SimplifyCFG IR pass during generic Scalar/IPO optimization 2020-08-06 13:16:00 -07:00
Generic [Tests] Be consistent w/definition of statepoint-example 2020-08-14 20:45:48 -07:00
Hexagon [Hexagon] Fix perfect shuffle generation for single vectors 2020-08-30 06:43:16 -05:00
Inputs
Lanai
MIR MIR: Infer not-SSA for subregister defs 2020-08-27 16:56:16 -04:00
MSP430
Mips GlobalISel: Add generic instructions for memory intrinsics 2020-08-26 20:08:45 -04:00
NVPTX [NVPTX] Fix typo in lit test 2020-08-17 16:02:11 -04:00
PowerPC [PowerPC] Implement builtins for xvcvspbf16 and xvcvbf16spn 2020-09-01 17:16:43 -05:00
RISCV [RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move 2020-08-27 10:32:22 +01:00
SPARC
SystemZ Revert "[BPI] Improve static heuristics for integer comparisons" 2020-08-17 20:44:33 +02:00
Thumb
Thumb2 [DAGCombiner] Fold an AND of a masked load into a zext_masked_load 2020-09-01 17:02:07 +01:00
VE [VE] Support f128 2020-08-17 17:26:52 +09:00
WebAssembly [SelectionDAG] Handle non-power-of-2 bitwidths in expandROT 2020-08-26 09:20:46 +01:00
WinCFGuard
WinEH
X86 [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle combining support 2020-09-02 09:24:46 +01:00
XCore