maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/MIR/ARM
History
Puyan Lotfi fe6c9cbb24 [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'. 
Planning to add support for named vregs. This puts is in a conundrum since
physregs are named as well. To rectify this we need to use a sigil other than
'%' for physregs in MIR. We've settled on using '$' for physregs but first we
must repurpose it from external symbols using it, which is what this commit is
all about. We think '&' will have familiar semantics for C/C++ users.

llvm-svn: 322146
 		2018-01-10 00:56:48 +00:00
..
PR32721_ifcvt_triangle_unanalyzable.mir [IfConversion] Add testcases [NFC] 2017-09-20 08:23:29 +00:00
bundled-instructions.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
cfi-same-value.mir [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'. 2018-01-10 00:56:48 +00:00
expected-closing-brace.mir
…
extraneous-closing-brace-error.mir
…
ifcvt_canFallThroughTo.mir [MIRPrinter] Print empty successor lists when they cannot be guessed 2017-09-19 23:34:12 +00:00
ifcvt_diamond_unanalyzable.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
ifcvt_forked_diamond_unanalyzable.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
ifcvt_simple_bad_zero_prob_succ.mir [IfConversion] Add testcases [NFC] 2017-09-20 08:23:29 +00:00
ifcvt_simple_unanalyzable.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
ifcvt_triangleWoCvtToNextEdge.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
lit.local.cfg
…
nested-instruction-bundle-error.mir
…
target-constant-pools-error.mir [MIR] Print target-specific constant pools 2017-08-02 11:09:30 +00:00