forked from OSchip/llvm-project
98 lines
3.6 KiB
C++
98 lines
3.6 KiB
C++
//===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVInstrInfo.h"
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#define GET_INSTRINFO_CTOR_DTOR
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#include "RISCVGenInstrInfo.inc"
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using namespace llvm;
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RISCVInstrInfo::RISCVInstrInfo()
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: RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP) {}
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void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DstReg,
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unsigned SrcReg, bool KillSrc) const {
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assert(RISCV::GPRRegClass.contains(DstReg, SrcReg) &&
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"Impossible reg-to-reg copy");
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BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.addImm(0);
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}
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void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned SrcReg, bool IsKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end())
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DL = I->getDebugLoc();
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if (RISCV::GPRRegClass.hasSubClassEq(RC))
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BuildMI(MBB, I, DL, get(RISCV::SW))
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.addReg(SrcReg, getKillRegState(IsKill))
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.addFrameIndex(FI)
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.addImm(0);
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else
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llvm_unreachable("Can't store this register to stack slot");
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}
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void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end())
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DL = I->getDebugLoc();
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if (RISCV::GPRRegClass.hasSubClassEq(RC))
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BuildMI(MBB, I, DL, get(RISCV::LW), DstReg).addFrameIndex(FI).addImm(0);
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else
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llvm_unreachable("Can't load this register from stack slot");
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}
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void RISCVInstrInfo::movImm32(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DstReg, uint64_t Val,
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MachineInstr::MIFlag Flag) const {
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assert(isInt<32>(Val) && "Can only materialize 32-bit constants");
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// TODO: If the value can be materialized using only one instruction, only
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// insert a single instruction.
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uint64_t Hi20 = ((Val + 0x800) >> 12) & 0xfffff;
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uint64_t Lo12 = SignExtend64<12>(Val);
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BuildMI(MBB, MBBI, DL, get(RISCV::LUI), DstReg)
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.addImm(Hi20)
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.setMIFlag(Flag);
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BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
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.addReg(DstReg, RegState::Kill)
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.addImm(Lo12)
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.setMIFlag(Flag);
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}
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