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AsmParser
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[RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlennonzero
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2017-12-15 10:20:51 +00:00 |
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Disassembler
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[RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention
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2017-12-13 09:57:25 +00:00 |
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InstPrinter
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[RISCV] Enable emission of alias instructions by default
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2017-12-15 09:47:01 +00:00 |
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MCTargetDesc
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Thread MCSubtargetInfo through Target::createMCAsmBackend
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2018-01-03 08:53:05 +00:00 |
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TargetInfo
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Fix RISCV build after r318352
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2017-11-16 18:39:31 +00:00 |
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CMakeLists.txt
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[RISCV] Add custom CC_RISCV calling convention and improved call support
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2017-12-11 12:49:02 +00:00 |
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LLVMBuild.txt
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCV.h
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[RISCV] Codegen support for memory operations on global addresses
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2017-11-08 13:24:21 +00:00 |
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RISCV.td
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[RISCV] Implement assembler pseudo instructions for RV32I and RV64I
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2017-12-12 15:46:15 +00:00 |
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RISCVAsmPrinter.cpp
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[RISCV] Add basic support for inline asm constraints
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2018-01-10 20:05:09 +00:00 |
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RISCVCallingConv.td
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[RISCV] Add custom CC_RISCV calling convention and improved call support
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2017-12-11 12:49:02 +00:00 |
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RISCVFrameLowering.cpp
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[RISCV] Support stack frames and offsets up to 32-bits
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2018-01-10 19:53:46 +00:00 |
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RISCVFrameLowering.h
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[RISCV] Implement prolog and epilog insertion
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2017-12-11 12:34:11 +00:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Add basic support for inline asm constraints
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2018-01-10 20:05:09 +00:00 |
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RISCVISelLowering.cpp
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[RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsics
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2018-01-10 20:12:00 +00:00 |
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RISCVISelLowering.h
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[RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsics
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2018-01-10 20:12:00 +00:00 |
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RISCVInstrFormats.td
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[RISCV] MC layer support for load/store instructions of the C (compressed) extension
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2017-12-07 12:50:32 +00:00 |
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RISCVInstrFormatsC.td
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[RISCV] MC layer support for the remaining RVC instructions
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2017-12-13 09:32:55 +00:00 |
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RISCVInstrInfo.cpp
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[RISCV] Support stack frames and offsets up to 32-bits
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2018-01-10 19:53:46 +00:00 |
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RISCVInstrInfo.h
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[RISCV] Support stack frames and offsets up to 32-bits
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2018-01-10 19:53:46 +00:00 |
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RISCVInstrInfo.td
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[RISCV] Define sfence.vma InstAliases to match the GNU RISC-V tools
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2017-12-13 12:46:55 +00:00 |
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RISCVInstrInfoA.td
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[RISCV] MC layer support for the standard RV64A instruction set extension
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2017-12-07 10:59:12 +00:00 |
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RISCVInstrInfoC.td
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[RISCV] Add Defs Uses information for c.jal and c.addi4spn
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2018-01-02 12:09:29 +00:00 |
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RISCVInstrInfoD.td
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[RISCV] Implement floating point assembler pseudo instructions
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2017-12-13 11:37:19 +00:00 |
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RISCVInstrInfoF.td
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[RISCV] Implement floating point assembler pseudo instructions
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2017-12-13 11:37:19 +00:00 |
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RISCVInstrInfoM.td
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[RISCV] MC layer support for the standard RV64M instruction set extension
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2017-12-07 10:56:07 +00:00 |
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RISCVMCInstLower.cpp
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[RISCV] Support and tests for a variety of additional LLVM IR constructs
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2017-11-21 08:11:03 +00:00 |
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RISCVMachineFunctionInfo.h
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[RISCV] Support for varargs
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2018-01-10 19:41:03 +00:00 |
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RISCVRegisterInfo.cpp
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[RISCV] Support stack frames and offsets up to 32-bits
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2018-01-10 19:53:46 +00:00 |
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RISCVRegisterInfo.h
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[RISCV] Support stack frames and offsets up to 32-bits
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2018-01-10 19:53:46 +00:00 |
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RISCVRegisterInfo.td
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[RISCV] MC layer support for the remaining RVC instructions
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2017-12-13 09:32:55 +00:00 |
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RISCVSubtarget.cpp
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVSubtarget.h
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[RISCV] MC layer support for load/store instructions of the C (compressed) extension
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2017-12-07 12:50:32 +00:00 |
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RISCVTargetMachine.cpp
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[RISCV] Fix 64-bit data layout mismatch between backend and target description
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2017-11-16 20:30:49 +00:00 |
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RISCVTargetMachine.h
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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