| .. |
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LoadStoreVectorizer.ll
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[NVPTX] Added support for .f16x2 instructions.
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2017-02-23 22:38:24 +00:00 |
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MachineSink-call.ll
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[NVPTX] Annotate call machine instructions as calls.
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2016-02-17 17:46:50 +00:00 |
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MachineSink-convergent.ll
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NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0
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2016-07-06 20:02:45 +00:00 |
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TailDuplication-convergent.ll
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NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0
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2016-07-06 20:02:45 +00:00 |
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access-non-generic.ll
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NVPTX: Move InferAddressSpaces to generic code
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2017-01-31 01:10:58 +00:00 |
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add-128bit.ll
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[DAGCombiner] add missing folds for scalar select of {-1,0,1}
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2017-02-24 17:17:33 +00:00 |
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addrspacecast-gvar.ll
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[NVPTX] Handle addrspacecast constant expressions in aggregate initializers
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2015-04-28 17:18:30 +00:00 |
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addrspacecast.ll
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[NVPTX] Remove NVPTXFavorNonGenericAddrSpaces pass.
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2016-10-31 21:51:42 +00:00 |
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aggr-param.ll
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…
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aggregate-return.ll
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[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.
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2017-02-21 22:56:05 +00:00 |
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alias.ll
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[CUDA] Die gracefully when trying to output an LLVM alias.
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2016-01-23 21:12:20 +00:00 |
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annotations.ll
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Whitespace cleanup in test/CodeGen/NVPTX/annotations.ll.
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2016-12-14 22:32:55 +00:00 |
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arg-lowering.ll
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…
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arithmetic-fp-sm20.ll
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…
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arithmetic-int.ll
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[NVPTX] expand mul_lohi to mul_lo and mul_hi
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2016-01-22 19:47:26 +00:00 |
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atomics-sm60.ll
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[NVPTX] Implement __nvvm_atom_add_gen_d builtin.
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2017-11-07 22:10:54 +00:00 |
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atomics-with-scope.ll
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[NVPTX] Added intrinsics for atom.gen.{sys|cta}.* instructions.
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2016-09-28 17:25:38 +00:00 |
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atomics.ll
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…
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barrier.ll
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[NVPTX] Implemented bar.warp.sync, barrier.sync, and vote{.sync} instructions/intrinsics/builtins.
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2017-09-21 18:44:49 +00:00 |
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bfe.ll
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…
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branch-fold.ll
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Roll forward r242871
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2015-07-29 18:59:09 +00:00 |
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bug17709.ll
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[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
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2017-05-15 17:17:44 +00:00 |
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bug21465.ll
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[NVPTX] Renamed NVPTXLowerKernelArgs -> NVPTXLowerArgs. NFC.
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2016-07-20 21:44:07 +00:00 |
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bug22246.ll
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…
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bug22322.ll
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Add address space mangling to lifetime intrinsics
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2017-04-10 20:18:21 +00:00 |
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bug26185-2.ll
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[NVPTX] Fix sign/zero-extending ldg/ldu instruction selection
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2016-05-02 18:12:02 +00:00 |
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bug26185.ll
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[NVPTX] Handle ldg created from sign-/zero-extended load
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2016-04-05 12:38:01 +00:00 |
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bypass-div.ll
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Use 32-bit divides instead of 64-bit divides where possible.
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2015-08-11 22:16:34 +00:00 |
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call-with-alloca-buffer.ll
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Fix NVPTX/call-with-alloca-buffer.ll after r276777.
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2016-07-26 18:28:33 +00:00 |
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callchain.ll
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…
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calling-conv.ll
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…
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combine-min-max.ll
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[NVPTX] Implement min/max in tablegen, rather than with custom DAGComine logic.
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2017-01-18 00:09:01 +00:00 |
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compare-int.ll
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…
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constant-vectors.ll
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…
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convergent-mir-call.ll
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[NVPTX] Use different, convergent MIs for convergent calls.
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2016-03-01 19:24:03 +00:00 |
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convert-fp.ll
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[NVPTX] Add fptosi tests to convert-fp.ll.
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2017-01-15 16:55:54 +00:00 |
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convert-int-sm20.ll
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…
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ctlz.ll
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[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
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2017-05-12 19:56:43 +00:00 |
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ctpop.ll
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[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
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2017-05-12 19:56:43 +00:00 |
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cttz.ll
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[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
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2017-05-12 19:56:43 +00:00 |
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disable-opt.ll
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[NVPTX] Disable performance optimizations when OptLevel==None
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2016-02-04 04:15:36 +00:00 |
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div-ri.ll
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…
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divrem-combine.ll
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[NVPTX] Compute 'rem' using the result of 'div', if possible.
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2016-10-28 21:44:00 +00:00 |
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envreg.ll
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…
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extloadv.ll
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[NVPTX] expand extload/truncstore for vectors of floats
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2015-07-01 21:32:42 +00:00 |
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f16-instructions.ll
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[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
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2017-05-15 17:17:44 +00:00 |
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f16x2-instructions.ll
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[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
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2017-05-15 17:17:44 +00:00 |
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fast-math.ll
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[NVPTX] Enable combineRepeatedFPDivisors for NVPTX.
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2017-02-03 15:13:50 +00:00 |
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fcos-no-fast-math.ll
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[NVPTX] Only lower sin/cos to approximate instructions if unsafe math is allowed.
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2017-01-13 18:48:13 +00:00 |
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fma-assoc.ll
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[DAGCombine] require UnsafeFPMath for re-association of addition
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2017-01-31 14:35:37 +00:00 |
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fma-disable.ll
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…
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fma.ll
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[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
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2017-05-15 17:17:44 +00:00 |
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fns.ll
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[NVPTX,CUDA] Added llvm.nvvm.fns intrinsic and matching __nvvm_fns builtin in clang.
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2017-12-06 17:50:05 +00:00 |
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fp-contract.ll
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…
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fp-literals.ll
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…
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fp16.ll
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…
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fsin-no-fast-math.ll
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[NVPTX] Only lower sin/cos to approximate instructions if unsafe math is allowed.
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2017-01-13 18:48:13 +00:00 |
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function-align.ll
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…
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generic-to-nvvm-ir.ll
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[Verifier] Remove the -verify-debug-info cl::opt
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2017-11-02 23:44:20 +00:00 |
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generic-to-nvvm.ll
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…
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global-addrspace.ll
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[NVPTX] Allow undef value as global initializer
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2015-08-22 05:40:26 +00:00 |
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global-ctor-empty.ll
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[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.
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2016-01-30 01:07:38 +00:00 |
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global-ctor.ll
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[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.
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2016-01-30 01:07:38 +00:00 |
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global-dtor.ll
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[CUDA] Die if we ask the NVPTX backend to emit a global ctor/dtor.
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2016-01-30 01:07:38 +00:00 |
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global-ordering.ll
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…
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global-variable-big.ll
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[NVPTX] Support global variables of integer type larger than i64.
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2017-01-18 00:29:53 +00:00 |
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global-visibility.ll
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[NVPTX] Do not emit .hidden or .protected directives as they are not allowed by PTX.
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2016-01-15 23:57:53 +00:00 |
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globals_init.ll
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The constant initialization for globals in NVPTX is generated as an
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2015-06-09 16:29:34 +00:00 |
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globals_lowering.ll
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Force relocation mode to be default, regardless of what is passed to the backend.
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2015-06-30 17:18:00 +00:00 |
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gvar-init.ll
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…
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half.ll
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[NVPTX] Added support for half-precision floating point.
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2017-01-13 20:56:17 +00:00 |
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i1-global.ll
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…
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i1-int-to-fp.ll
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…
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i1-param.ll
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…
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i8-param.ll
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[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
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2017-05-15 17:17:44 +00:00 |
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i128-global.ll
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[NVPTX] Add lowering of i128 params.
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2017-07-20 21:16:03 +00:00 |
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i128-param.ll
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[NVPTX] Add lowering of i128 params.
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2017-07-20 21:16:03 +00:00 |
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i128-retval.ll
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[NVPTX] Add lowering of i128 params.
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2017-07-20 21:16:03 +00:00 |
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idioms.ll
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[NVPTX] Lower integer absolute value idiom to abs instruction.
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2017-01-18 00:08:44 +00:00 |
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imad.ll
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…
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implicit-def.ll
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…
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inline-asm.ll
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…
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intrin-nocapture.ll
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Reapply 239795 - [InstCombine] Propagate non-null facts to call parameters
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2015-06-16 20:24:25 +00:00 |
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intrinsic-old.ll
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[NVVMIntrRange] Only set range metadata if none is already present
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2016-12-22 00:51:59 +00:00 |
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intrinsics.ll
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Fix some broken CHECK lines.
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2017-01-22 20:28:56 +00:00 |
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isspacep.ll
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…
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ld-addrspace.ll
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…
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ld-generic.ll
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…
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ld-st-addrrspace.py
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[NVPTX] allow address space inference for volatile loads/stores.
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2017-10-24 20:31:44 +00:00 |
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ldg-invariant.ll
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[NVPTX] Add tests that invariant vector loads get lowered to ld.global.nc.
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2017-02-04 01:54:56 +00:00 |
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ldparam-v4.ll
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[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.
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2017-02-21 22:56:05 +00:00 |
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ldu-i8.ll
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…
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ldu-ldg.ll
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…
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ldu-reg-plus-offset.ll
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…
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lit.local.cfg
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…
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load-sext-i1.ll
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…
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load-with-non-coherent-cache.ll
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[NVPTX] Use LDG for pointer induction variables.
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2015-08-05 23:11:57 +00:00 |
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local-stack-frame.ll
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[NVPTX] Move NVPTXPeephole after NVPTXPrologEpilogPass
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2015-07-01 20:08:06 +00:00 |
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loop-vectorize.ll
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[NVPTX] declare no vector registers
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2015-07-10 04:31:56 +00:00 |
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lower-aggr-copies.ll
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[Memcpy Loop Lowering] Remove the fixed int8 lowering.
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2017-12-18 15:31:14 +00:00 |
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lower-alloca.ll
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NVPTX: Move InferAddressSpaces to generic code
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2017-01-31 01:10:58 +00:00 |
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lower-kernel-ptr-arg.ll
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[NVPTX] Improve lowering of byval args of device functions.
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2016-07-20 18:39:47 +00:00 |
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machine-sink.ll
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…
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managed.ll
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…
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match.ll
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[NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.
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2017-09-26 17:07:23 +00:00 |
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math-intrins.ll
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[NVPTX] Add codegen tests for llvm.fma.
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2017-01-15 16:55:37 +00:00 |
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minmax-negative.ll
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Improve clamp recognition in ValueTracking.
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2017-10-27 20:53:41 +00:00 |
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misaligned-vector-ldst.ll
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[NVPTX] Fixed lowering of unaligned loads/stores of f16 scalars and vectors.
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2017-03-07 20:33:38 +00:00 |
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module-inline-asm.ll
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…
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mulwide.ll
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…
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named-barriers.ll
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[NVPTX] Add intrinsics to support named barriers.
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2017-01-28 16:38:15 +00:00 |
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noduplicate-syncthreads.ll
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NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0
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2016-07-06 20:02:45 +00:00 |
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nounroll.ll
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…
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nvcl-param-align.ll
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…
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nvvm-reflect-module-flag.ll
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[NVPTX] Read __CUDA_FTZ from module flags in NVVMReflect.
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2016-04-01 01:09:07 +00:00 |
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nvvm-reflect.ll
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[NVPTX] Let there be One True Way to set NVVMReflect params.
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2017-01-15 16:54:35 +00:00 |
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param-align.ll
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[NVPTX] Make sure we adjust alignment at all call sites
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2016-07-18 21:58:48 +00:00 |
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param-load-store.ll
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[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
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2017-05-15 17:17:44 +00:00 |
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pr13291-i1-store.ll
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[NVPTX] roll forward r239082
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2015-06-04 21:28:26 +00:00 |
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pr16278.ll
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…
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pr17529.ll
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…
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refl1.ll
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…
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reg-copy.ll
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[NVPTX] allow register copy between float and int
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2015-08-01 18:02:12 +00:00 |
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reg-types.ll
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[NVPTX] Use untyped (.b) integer registers in PTX.
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2016-08-12 22:02:19 +00:00 |
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rotate.ll
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…
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sched1.ll
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Only enable LiveRangeShrink for x86.
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2017-05-17 20:18:13 +00:00 |
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sched2.ll
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Only enable LiveRangeShrink for x86.
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2017-05-17 20:18:13 +00:00 |
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sext-in-reg.ll
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…
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sext-params.ll
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…
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shfl-sync.ll
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[NVPTX] Implemented shfl.sync instruction and supporting intrinsics/builtins.
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2017-09-20 21:23:07 +00:00 |
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shfl.ll
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[NVPTX] Remove NVPTXFavorNonGenericAddrSpaces pass.
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2016-10-31 21:51:42 +00:00 |
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shift-parts.ll
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…
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simple-call.ll
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[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
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2017-05-15 17:17:44 +00:00 |
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sm-version-20.ll
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…
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sm-version-21.ll
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…
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sm-version-30.ll
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…
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sm-version-32.ll
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…
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sm-version-35.ll
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…
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sm-version-37.ll
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…
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sm-version-50.ll
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…
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sm-version-52.ll
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…
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sm-version-53.ll
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…
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sm-version-60.ll
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[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.
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2016-07-06 21:06:10 +00:00 |
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sm-version-61.ll
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[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.
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2016-07-06 21:06:10 +00:00 |
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sm-version-62.ll
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[NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.
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2016-07-06 21:06:10 +00:00 |
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sm-version-70.ll
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[CUDA] Added rudimentary support for CUDA-9 and sm_70.
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2017-09-07 18:14:32 +00:00 |
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speculative-execution-divergent-target.ll
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Move divergent-target test into CodeGen/NVPTX because it requires an NVPTX target.
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2016-04-15 01:20:52 +00:00 |
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sqrt-approx.ll
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[NVPTX] Compute approx sqrt as 1/rsqrt(x) rather than x*rsqrt(x).
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2017-01-31 23:08:57 +00:00 |
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st-addrspace.ll
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…
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st-generic.ll
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…
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surf-read-cuda.ll
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[NVPTX] roll forward r239082
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2015-06-04 21:28:26 +00:00 |
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surf-read.ll
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…
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surf-write-cuda.ll
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…
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surf-write.ll
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…
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symbol-naming.ll
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[NVPTX] Assign valid global names
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2017-12-04 14:19:33 +00:00 |
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tex-read-cuda.ll
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[NVPTX] roll forward r239082
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2015-06-04 21:28:26 +00:00 |
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tex-read.ll
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…
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texsurf-queries.ll
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…
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tid-range.ll
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[SelectionDAG] Correctly transform range metadata to AssertZExt
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2017-01-06 00:11:46 +00:00 |
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tuple-literal.ll
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…
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vec-param-load.ll
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[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.
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2017-02-21 22:56:05 +00:00 |
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vec8.ll
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Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."
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2017-05-18 18:50:05 +00:00 |
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vector-args.ll
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…
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vector-call.ll
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[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
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2017-05-15 17:17:44 +00:00 |
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vector-compare.ll
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…
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vector-global.ll
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…
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vector-loads.ll
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…
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vector-select.ll
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…
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vector-stores.ll
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…
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vote.ll
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[NVPTX] Implemented bar.warp.sync, barrier.sync, and vote{.sync} instructions/intrinsics/builtins.
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2017-09-21 18:44:49 +00:00 |
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weak-global.ll
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…
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weak-linkage.ll
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…
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wmma.py
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[NVPTX] Implemented wmma intrinsics and instructions.
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2017-10-12 18:27:55 +00:00 |
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zero-cs.ll
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llvm/test/CodeGen/NVPTX/zero-cs.ll: Relax an expression to match in -Asserts.
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2016-09-21 04:43:11 +00:00 |
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zeroext-32bit.ll
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[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
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2017-05-15 17:17:44 +00:00 |
7212b6e4b9