forked from OSchip/llvm-project
b109d51865
Selected: the InstructionSelect pass ran and all pre-isel generic instructions have been eliminated; i.e., all instructions are now target-specific or non-pre-isel generic instructions (e.g., COPY). Since only pre-isel generic instructions can have generic virtual register operands, this also means that all generic virtual registers have been constrained to virtual registers (assigned to register classes) and that all sizes attached to them have been eliminated. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277482 |
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AArch64 | ||
AMDGPU | ||
ARM | ||
Generic | ||
Hexagon | ||
Lanai | ||
Mips | ||
NVPTX | ||
PowerPC | ||
X86 |