llvm-project/llvm/test/CodeGen/MIR
Ahmed Bougacha b109d51865 [GlobalISel] Add Selected MachineFunction property.
Selected: the InstructionSelect pass ran and all pre-isel generic
instructions have been eliminated; i.e., all instructions are now
target-specific or non-pre-isel generic instructions (e.g., COPY).

Since only pre-isel generic instructions can have generic virtual register
operands, this also means that all generic virtual registers have been
constrained to virtual registers (assigned to register classes) and that
all sizes attached to them have been eliminated.

This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.

llvm-svn: 277482
2016-08-02 16:49:19 +00:00
..
AArch64 [AArch64] Return the correct size for TLSDESC_CALLSEQ 2016-08-01 08:38:49 +00:00
AMDGPU CodeGen: add new "intrinsic" MachineOperand kind. 2016-07-29 20:32:59 +00:00
ARM MIRParser: Use shorter cfi identifiers 2016-07-26 18:20:00 +00:00
Generic [GlobalISel] Add Selected MachineFunction property. 2016-08-02 16:49:19 +00:00
Hexagon [MIR] Print on the given output instead of stderr. 2016-07-13 20:36:03 +00:00
Lanai [MIR] Print on the given output instead of stderr. 2016-07-13 20:36:03 +00:00
Mips MIRParser: Use shorter cfi identifiers 2016-07-26 18:20:00 +00:00
NVPTX llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
PowerPC llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
X86 [MIRParser] Accept unsized generic instructions. 2016-07-28 17:15:12 +00:00