..
AsmParser
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
Disassembler
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
MCTargetDesc
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
CMakeLists.txt
[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
2021-09-20 09:39:44 -07:00
RISCV.h
[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
2021-09-20 09:39:44 -07:00
RISCV.td
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
RISCVAsmPrinter.cpp
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVCallingConv.td
…
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
Revert "[RISCV] Add an GPR def to the Zvlseg SPILL/RELOAD pseudos"
2021-10-02 10:44:11 -07:00
RISCVFrameLowering.cpp
[NFC] Add doxygen comment for hasFp in RISCVFrameLowering.cpp
2021-10-06 22:35:28 +05:30
RISCVFrameLowering.h
[RISCV] Enable shrink wrap by default
2021-09-02 09:47:58 -05:00
RISCVGatherScatterLowering.cpp
[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
2021-09-20 09:39:44 -07:00
RISCVISelDAGToDAG.cpp
[RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.
2021-10-05 21:49:54 +08:00
RISCVISelDAGToDAG.h
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
RISCVISelLowering.cpp
[RISCV] Handle vector of pointer in getTgtMemIntrinsic for strided load/store.
2021-10-07 10:11:56 -07:00
RISCVISelLowering.h
[RISCV][VP] Add support for VP_REDUCE_* operations
2021-09-23 11:11:05 +01:00
RISCVInsertVSETVLI.cpp
[RISCV] (1/2) Add the tail policy argument to builtins/intrinsics.
2021-09-24 17:09:50 +08:00
RISCVInstrFormats.td
[RISCV] Initial support .insn directive for the assembler.
2021-09-12 15:56:12 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrInfo.cpp
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
RISCVInstrInfo.h
[TII] Remove the MFI argument to convertToThreeAddress. NFC.
2021-09-23 08:58:46 +01:00
RISCVInstrInfo.td
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
RISCVInstrInfoA.td
[RISCV][NFC] Add explicit type i64 to RV64 only patterns.
2021-04-09 09:37:04 +08:00
RISCVInstrInfoC.td
…
RISCVInstrInfoD.td
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
2021-08-07 16:06:00 -07:00
RISCVInstrInfoF.td
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
2021-08-07 16:06:00 -07:00
RISCVInstrInfoM.td
[RISCV] Select (srl (sext_inreg X, i32), uimm5) to SRAIW if only lower 32 bits are used.
2021-09-16 11:03:35 -07:00
RISCVInstrInfoV.td
[RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change
2021-10-12 06:46:46 +00:00
RISCVInstrInfoVPseudos.td
[RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change
2021-10-12 06:46:46 +00:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Update to vlm.v and vsm.v according to v1.0-rc1.
2021-10-05 21:49:54 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Rename assembler mnemonic of unordered floating-point reductions for v1.0-rc change
2021-10-12 06:46:46 +00:00
RISCVInstrInfoZb.td
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
RISCVInstrInfoZfh.td
[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.
2021-08-07 16:06:00 -07:00
RISCVInstructionSelector.cpp
…
RISCVLegalizerInfo.cpp
[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one
2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
…
RISCVMCInstLower.cpp
[RISCV] Remove the _COMMUTABLE and _TA versions of FMA and wide FMA vector instructions.
2021-08-04 10:39:50 -07:00
RISCVMachineFunctionInfo.h
[RISCV] Don't emit save-restore call if function is a interrupt handler
2021-04-16 12:54:47 +08:00
RISCVMergeBaseOffset.cpp
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
RISCVRegisterBankInfo.cpp
…
RISCVRegisterBankInfo.h
…
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
[RISCV] Reserve an emergency spill slot for any RVV spills
2021-06-03 10:44:34 +01:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
[RISCV] Initial support .insn directive for the assembler.
2021-09-12 15:56:12 -07:00
RISCVSchedRocket.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVSchedSiFive7.td
[RISCV] Fix typo in RISCVSchedSiFive7.td
2021-09-01 16:39:48 -05:00
RISCVSchedule.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVScheduleB.td
[RISCV] Move scheduling resources for B into a separate file (NFC)
2021-03-29 20:37:22 -05:00
RISCVScheduleV.td
[RISCV] Add scheduling resources for V
2021-08-03 15:47:51 -05:00
RISCVSubtarget.cpp
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
RISCVSubtarget.h
[RISCV] Remove experimental-b extension that includes all Zb* extensions
2021-10-07 20:47:17 -07:00
RISCVSystemOperands.td
RISCV: add a few deprecated aliases for CSRs
2021-05-21 13:52:58 -07:00
RISCVTargetMachine.cpp
Move TargetRegistry.(h|cpp) from Support to MC
2021-10-08 14:51:48 -07:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Add zext.h/zext.w to RISCVTTIImpl::getIntImmCostInst.
2021-08-18 09:40:40 -07:00
RISCVTargetTransformInfo.h
[RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.
2021-09-20 09:39:44 -07:00
0608bbd4e8