forked from OSchip/llvm-project
158 lines
6.2 KiB
C++
158 lines
6.2 KiB
C++
//===-- LanaiISelLowering.h - Lanai DAG Lowering Interface -....-*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Lanai uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
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#define LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
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#include "Lanai.h"
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#include "LanaiRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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namespace LanaiISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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ADJDYNALLOC,
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// Return with a flag operand. Operand 0 is the chain operand.
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RET_FLAG,
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// CALL - These operations represent an abstract call instruction, which
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// includes a bunch of information.
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CALL,
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// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
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// is condition code and operand 4 is flag operand.
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SELECT_CC,
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// SETCC - Store the conditional code to a register.
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SETCC,
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// SET_FLAG - Set flag compare.
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SET_FLAG,
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// SUBBF - Subtract with borrow that sets flags.
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SUBBF,
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// BR_CC - Used to glue together a conditional branch and comparison
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BR_CC,
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// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
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// and TargetGlobalAddress.
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Wrapper,
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// Get the Higher/Lower 16 bits from a 32-bit immediate.
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HI,
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LO,
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// Small 21-bit immediate in global memory.
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SMALL
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};
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} // namespace LanaiISD
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class LanaiSubtarget;
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class LanaiTargetLowering : public TargetLowering {
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public:
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LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI);
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// LowerOperation - Provide custom lowering hooks for some operations.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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// getTargetNodeName - This method returns the name of a target specific
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// DAG node.
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const char *getTargetNodeName(unsigned Opcode) const override;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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Register getRegisterByName(const char *RegName, LLT VT,
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const MachineFunction &MF) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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ConstraintWeight
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getSingleConstraintMatchWeight(AsmOperandInfo &Info,
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const char *Constraint) const override;
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void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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private:
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SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool IsVarArg,
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bool IsTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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const LanaiRegisterInfo *TRI;
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H
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