forked from OSchip/llvm-project
372 lines
14 KiB
TableGen
372 lines
14 KiB
TableGen
//===-- RISCVInstrInfoFH.td - RISC-V 'FH' instructions -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'Zfh'
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// half-precision floating-point extension, version 0.1.
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// This version is still experimental as the 'Zfh' extension hasn't been
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// ratified yet.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RISC-V specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def SDT_RISCVFMV_H_X
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: SDTypeProfile<1, 1, [SDTCisVT<0, f16>, SDTCisVT<1, XLenVT>]>;
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def SDT_RISCVFMV_X_ANYEXTH
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: SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, f16>]>;
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def riscv_fmv_h_x
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: SDNode<"RISCVISD::FMV_H_X", SDT_RISCVFMV_H_X>;
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def riscv_fmv_x_anyexth
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: SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_ANYEXTH>;
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPFMAH_rrr_frm<RISCVOpcode opcode, string opcodestr>
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: RVInstR4<0b10, opcode, (outs FPR16:$rd),
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(ins FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, frmarg:$funct3),
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opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
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class FPFMAHDynFrmAlias<FPFMAH_rrr_frm Inst, string OpcodeStr>
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: InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
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(Inst FPR16:$rd, FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPALUH_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
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: RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR16:$rd),
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(ins FPR16:$rs1, FPR16:$rs2), opcodestr, "$rd, $rs1, $rs2">;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPALUH_rr_frm<bits<7> funct7, string opcodestr>
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: RVInstRFrm<funct7, OPC_OP_FP, (outs FPR16:$rd),
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(ins FPR16:$rs1, FPR16:$rs2, frmarg:$funct3), opcodestr,
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"$rd, $rs1, $rs2, $funct3">;
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class FPALUHDynFrmAlias<FPALUH_rr_frm Inst, string OpcodeStr>
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: InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
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(Inst FPR16:$rd, FPR16:$rs1, FPR16:$rs2, 0b111)>;
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
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class FPCmpH_rr<bits<3> funct3, string opcodestr>
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: RVInstR<0b1010010, funct3, OPC_OP_FP, (outs GPR:$rd),
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(ins FPR16:$rs1, FPR16:$rs2), opcodestr, "$rd, $rs1, $rs2">,
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Sched<[]>;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZfh] in {
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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def FLH : RVInstI<0b001, OPC_LOAD_FP, (outs FPR16:$rd),
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(ins GPR:$rs1, simm12:$imm12),
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"flh", "$rd, ${imm12}(${rs1})">,
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Sched<[]>;
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// Operands for stores are in the order srcreg, base, offset rather than
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// reflecting the order these fields are specified in the instruction
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// encoding.
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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def FSH : RVInstS<0b001, OPC_STORE_FP, (outs),
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(ins FPR16:$rs2, GPR:$rs1, simm12:$imm12),
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"fsh", "$rs2, ${imm12}(${rs1})">,
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Sched<[]>;
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def FMADD_H : FPFMAH_rrr_frm<OPC_MADD, "fmadd.h">,
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Sched<[]>;
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def : FPFMAHDynFrmAlias<FMADD_H, "fmadd.h">;
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def FMSUB_H : FPFMAH_rrr_frm<OPC_MSUB, "fmsub.h">,
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Sched<[]>;
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def : FPFMAHDynFrmAlias<FMSUB_H, "fmsub.h">;
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def FNMSUB_H : FPFMAH_rrr_frm<OPC_NMSUB, "fnmsub.h">,
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Sched<[]>;
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def : FPFMAHDynFrmAlias<FNMSUB_H, "fnmsub.h">;
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def FNMADD_H : FPFMAH_rrr_frm<OPC_NMADD, "fnmadd.h">,
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Sched<[]>;
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def : FPFMAHDynFrmAlias<FNMADD_H, "fnmadd.h">;
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def FADD_H : FPALUH_rr_frm<0b0000010, "fadd.h">,
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Sched<[]>;
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def : FPALUHDynFrmAlias<FADD_H, "fadd.h">;
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def FSUB_H : FPALUH_rr_frm<0b0000110, "fsub.h">,
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Sched<[]>;
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def : FPALUHDynFrmAlias<FSUB_H, "fsub.h">;
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def FMUL_H : FPALUH_rr_frm<0b0001010, "fmul.h">,
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Sched<[]>;
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def : FPALUHDynFrmAlias<FMUL_H, "fmul.h">;
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def FDIV_H : FPALUH_rr_frm<0b0001110, "fdiv.h">,
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Sched<[]>;
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def : FPALUHDynFrmAlias<FDIV_H, "fdiv.h">;
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def FSQRT_H : FPUnaryOp_r_frm<0b0101110, FPR16, FPR16, "fsqrt.h">,
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Sched<[]> {
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let rs2 = 0b00000;
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}
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def : FPUnaryOpDynFrmAlias<FSQRT_H, "fsqrt.h", FPR16, FPR16>;
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def FSGNJ_H : FPALUH_rr<0b0010010, 0b000, "fsgnj.h">,
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Sched<[]>;
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def FSGNJN_H : FPALUH_rr<0b0010010, 0b001, "fsgnjn.h">,
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Sched<[]>;
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def FSGNJX_H : FPALUH_rr<0b0010010, 0b010, "fsgnjx.h">,
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Sched<[]>;
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def FMIN_H : FPALUH_rr<0b0010110, 0b000, "fmin.h">,
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Sched<[]>;
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def FMAX_H : FPALUH_rr<0b0010110, 0b001, "fmax.h">,
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Sched<[]>;
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def FCVT_W_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.w.h">,
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Sched<[]> {
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let rs2 = 0b00000;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_W_H, "fcvt.w.h", GPR, FPR16>;
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def FCVT_WU_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.wu.h">,
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Sched<[]> {
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let rs2 = 0b00001;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_WU_H, "fcvt.wu.h", GPR, FPR16>;
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def FCVT_H_W : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.w">,
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Sched<[]> {
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let rs2 = 0b00000;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_H_W, "fcvt.h.w", FPR16, GPR>;
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def FCVT_H_WU : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.wu">,
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Sched<[]> {
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let rs2 = 0b00001;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_H_WU, "fcvt.h.wu", FPR16, GPR>;
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def FCVT_H_S : FPUnaryOp_r_frm<0b0100010, FPR16, FPR32, "fcvt.h.s">,
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Sched<[]> {
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let rs2 = 0b00000;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_H_S, "fcvt.h.s", FPR16, FPR32>;
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def FCVT_S_H : FPUnaryOp_r<0b0100000, 0b000, FPR32, FPR16, "fcvt.s.h">,
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Sched<[]> {
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let rs2 = 0b00010;
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}
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def FMV_X_H : FPUnaryOp_r<0b1110010, 0b000, GPR, FPR16, "fmv.x.h">,
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Sched<[]> {
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let rs2 = 0b00000;
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}
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def FMV_H_X : FPUnaryOp_r<0b1111010, 0b000, FPR16, GPR, "fmv.h.x">,
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Sched<[]> {
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let rs2 = 0b00000;
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}
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def FEQ_H : FPCmpH_rr<0b010, "feq.h">;
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def FLT_H : FPCmpH_rr<0b001, "flt.h">;
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def FLE_H : FPCmpH_rr<0b000, "fle.h">;
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def FCLASS_H : FPUnaryOp_r<0b1110010, 0b001, GPR, FPR16, "fclass.h">,
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Sched<[]> {
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let rs2 = 0b00000;
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}
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} // Predicates = [HasStdExtZfh]
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let Predicates = [HasStdExtZfh, IsRV64] in {
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def FCVT_L_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.l.h">,
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Sched<[]> {
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let rs2 = 0b00010;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_L_H, "fcvt.l.h", GPR, FPR16>;
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def FCVT_LU_H : FPUnaryOp_r_frm<0b1100010, GPR, FPR16, "fcvt.lu.h">,
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Sched<[]> {
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let rs2 = 0b00011;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_LU_H, "fcvt.lu.h", GPR, FPR16>;
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def FCVT_H_L : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.l">,
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Sched<[]> {
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let rs2 = 0b00010;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_H_L, "fcvt.h.l", FPR16, GPR>;
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def FCVT_H_LU : FPUnaryOp_r_frm<0b1101010, FPR16, GPR, "fcvt.h.lu">,
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Sched<[]> {
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let rs2 = 0b00011;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_H_LU, "fcvt.h.lu", FPR16, GPR>;
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} // Predicates = [HasStdExtZfh, IsRV64]
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let Predicates = [HasStdExtZfh, HasStdExtD] in {
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def FCVT_H_D : FPUnaryOp_r_frm<0b0100010, FPR16, FPR64, "fcvt.h.d">,
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Sched<[]> {
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let rs2 = 0b00001;
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}
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def : FPUnaryOpDynFrmAlias<FCVT_H_D, "fcvt.h.d", FPR16, FPR64>;
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def FCVT_D_H : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR16, "fcvt.d.h">,
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Sched<[]> {
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let rs2 = 0b00010;
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}
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} // Predicates = [HasStdExtZfh, HasStdExtD]
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZfh] in {
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def : InstAlias<"flh $rd, (${rs1})", (FLH FPR16:$rd, GPR:$rs1, 0), 0>;
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def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>;
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def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>;
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def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>;
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def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>;
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// fgt.h/fge.h are recognised by the GNU assembler but the canonical
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// flt.h/fle.h forms will always be printed. Therefore, set a zero weight.
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def : InstAlias<"fgt.h $rd, $rs, $rt",
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(FLT_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
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def : InstAlias<"fge.h $rd, $rs, $rt",
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(FLE_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
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def PseudoFLH : PseudoFloatLoad<"flh", FPR16>;
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def PseudoFSH : PseudoStore<"fsh", FPR16>;
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} // Predicates = [HasStdExtZfh]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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/// Generic pattern classes
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class PatFpr16Fpr16<SDPatternOperator OpNode, RVInstR Inst>
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: Pat<(OpNode FPR16:$rs1, FPR16:$rs2), (Inst $rs1, $rs2)>;
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class PatFpr16Fpr16DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
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: Pat<(OpNode FPR16:$rs1, FPR16:$rs2), (Inst $rs1, $rs2, 0b111)>;
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let Predicates = [HasStdExtZfh] in {
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/// Float constants
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def : Pat<(f16 (fpimm0)), (FMV_H_X X0)>;
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/// Float conversion operations
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// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
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// are defined later.
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/// Float arithmetic operations
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def : PatFpr16Fpr16DynFrm<fadd, FADD_H>;
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def : PatFpr16Fpr16DynFrm<fsub, FSUB_H>;
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def : PatFpr16Fpr16DynFrm<fmul, FMUL_H>;
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def : PatFpr16Fpr16DynFrm<fdiv, FDIV_H>;
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def : Pat<(fsqrt FPR16:$rs1), (FSQRT_H FPR16:$rs1, 0b111)>;
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def : Pat<(fneg FPR16:$rs1), (FSGNJN_H $rs1, $rs1)>;
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def : Pat<(fabs FPR16:$rs1), (FSGNJX_H $rs1, $rs1)>;
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def : PatFpr16Fpr16<fcopysign, FSGNJ_H>;
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def : Pat<(fcopysign FPR16:$rs1, (fneg FPR16:$rs2)), (FSGNJN_H $rs1, $rs2)>;
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def : Pat<(fcopysign FPR16:$rs1, FPR32:$rs2),
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(FSGNJ_H $rs1, (FCVT_H_S $rs2, 0b111))>;
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def : Pat<(fcopysign FPR16:$rs1, FPR64:$rs2),
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(FSGNJ_H $rs1, (FCVT_H_D $rs2, 0b111))>;
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def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>;
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def : Pat<(fcopysign FPR64:$rs1, FPR16:$rs2), (FSGNJ_D $rs1, (FCVT_D_H $rs2))>;
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// fmadd: rs1 * rs2 + rs3
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def : Pat<(fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3),
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(FMADD_H $rs1, $rs2, $rs3, 0b111)>;
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// fmsub: rs1 * rs2 - rs3
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def : Pat<(fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3)),
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(FMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
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// fnmsub: -rs1 * rs2 + rs3
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def : Pat<(fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3),
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(FNMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
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// fnmadd: -rs1 * rs2 - rs3
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def : Pat<(fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3)),
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(FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
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def : PatFpr16Fpr16<fminnum, FMIN_H>;
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def : PatFpr16Fpr16<fmaxnum, FMAX_H>;
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/// Setcc
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def : PatFpr16Fpr16<seteq, FEQ_H>;
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def : PatFpr16Fpr16<setoeq, FEQ_H>;
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def : PatFpr16Fpr16<setlt, FLT_H>;
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def : PatFpr16Fpr16<setolt, FLT_H>;
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def : PatFpr16Fpr16<setle, FLE_H>;
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def : PatFpr16Fpr16<setole, FLE_H>;
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def Select_FPR16_Using_CC_GPR : SelectCC_rrirr<FPR16, GPR>;
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/// Loads
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defm : LdPat<load, FLH, f16>;
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/// Stores
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defm : StPat<store, FSH, FPR16, f16>;
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/// Float conversion operations
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// f32 -> f16, f16 -> f32
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def : Pat<(fpround FPR32:$rs1), (FCVT_H_S FPR32:$rs1, 0b111)>;
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def : Pat<(fpextend FPR16:$rs1), (FCVT_S_H FPR16:$rs1)>;
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// Moves (no conversion)
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def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>;
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def : Pat<(riscv_fmv_x_anyexth FPR16:$src), (FMV_X_H FPR16:$src)>;
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} // Predicates = [HasStdExtZfh]
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let Predicates = [HasStdExtZfh, IsRV32] in {
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// float->[u]int. Round-to-zero must be used.
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def : Pat<(i32 (fp_to_sint FPR16:$rs1)), (FCVT_W_H $rs1, 0b001)>;
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def : Pat<(i32 (fp_to_uint FPR16:$rs1)), (FCVT_WU_H $rs1, 0b001)>;
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// [u]int->float. Match GCC and default to using dynamic rounding mode.
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def : Pat<(sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W $rs1, 0b111)>;
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def : Pat<(uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU $rs1, 0b111)>;
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} // Predicates = [HasStdExtZfh, IsRV32]
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let Predicates = [HasStdExtZfh, IsRV64] in {
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// FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
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// because fpto[u|s]i produces poison if the value can't fit into the target.
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// We match the single case below because fcvt.wu.s sign-extends its result so
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// is cheaper than fcvt.lu.h+sext.w.
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def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR16:$rs1)), i32),
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(FCVT_WU_H $rs1, 0b001)>;
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// FP->[u]int64
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def : Pat<(i64 (fp_to_sint FPR16:$rs1)), (FCVT_L_H $rs1, 0b001)>;
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def : Pat<(i64 (fp_to_uint FPR16:$rs1)), (FCVT_LU_H $rs1, 0b001)>;
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// [u]int->fp. Match GCC and default to using dynamic rounding mode.
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def : Pat<(sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W $rs1, 0b111)>;
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def : Pat<(uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU $rs1, 0b111)>;
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def : Pat<(sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L $rs1, 0b111)>;
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def : Pat<(uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU $rs1, 0b111)>;
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} // Predicates = [HasStdExtZfh, IsRV64]
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let Predicates = [HasStdExtZfh, HasStdExtD] in {
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/// Float conversion operations
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// f64 -> f16, f16 -> f64
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def : Pat<(fpround FPR64:$rs1), (FCVT_H_D FPR64:$rs1, 0b111)>;
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def : Pat<(fpextend FPR16:$rs1), (FCVT_D_H FPR16:$rs1)>;
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}
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