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llvm-project/mlir/lib/Conversion
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Rob Suderman ceeb5b0f87 [mlir][tosa] Add tosa.max_pool2d lowering to linalg int max pooling additions 
Lowerings tosa.max_pool2d to linalg equivalent operations. Includes
adding max pooling operations for linalg, with corresponding tests.

Differential Revision: https://reviews.llvm.org/D99824
 		2021-04-08 18:17:16 -07:00
..
AffineToStandard [mlir] Fix support for lowering non-32-bit affine reductions. 2021-04-06 14:00:15 +02:00
ArmSVEToLLVM [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
AsyncToLLVM Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
ComplexToLLVM [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
GPUCommon Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
GPUToNVVM [mlir] introduce data layout entry for index type 2021-03-24 15:13:42 +01:00
GPUToROCDL [mlir] introduce data layout entry for index type 2021-03-24 15:13:42 +01:00
GPUToSPIRV [mlir][spirv] Add utilities for push constant value 2021-04-02 07:51:07 -04:00
GPUToVulkan Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
LinalgToLLVM Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
LinalgToSPIRV [mlir][spirv] Add utilities for push constant value 2021-04-02 07:51:07 -04:00
LinalgToStandard Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
OpenMPToLLVM [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
PDLToPDLInterp [mlir][pdl] Cast the OperationPosition to Position to fix MSVC miscompile 2021-03-16 16:11:14 -07:00
SCFToGPU [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
SCFToOpenMP Rename FrozenRewritePatternList -> FrozenRewritePatternSet; NFC. 2021-03-22 17:40:45 -07:00
SCFToSPIRV [mlir][spirv] Add utilities for push constant value 2021-04-02 07:51:07 -04:00
SCFToStandard [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
SPIRVToLLVM Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
ShapeToStandard Define a `NoTerminator` traits that allows operations with a single block region to not provide a terminator 2021-03-25 03:59:03 +00:00
StandardToLLVM [mlir] introduce data layout entry for index type 2021-03-24 15:13:42 +01:00
StandardToSPIRV [mlir][StandardToSPIRV] Handle i1 case for lowering memref.load/store op 2021-04-08 12:15:25 -07:00
TosaToLinalg [mlir][tosa] Add tosa.max_pool2d lowering to linalg int max pooling additions 2021-04-08 18:17:16 -07:00
TosaToSCF [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
TosaToStandard [PatternMatch] Big mechanical rename OwningRewritePatternList -> RewritePatternSet and insert -> add. NFC 2021-03-22 17:20:50 -07:00
VectorToLLVM [mlir] add support for index type in vectors. 2021-04-08 08:17:13 +00:00
VectorToROCDL [mlir] Add "mask" operand to vector.transfer_read/write. 2021-04-07 21:33:13 +09:00
VectorToSCF [mlir] Add "mask" operand to vector.transfer_read/write. 2021-04-07 21:33:13 +09:00
VectorToSPIRV [mlir][spirv] Add utilities for push constant value 2021-04-02 07:51:07 -04:00
CMakeLists.txt [mlir] squash LLVM_AVX512 dialect into AVX512 2021-03-10 13:07:26 +01:00
PassDetail.h [mlir][amx] Add Intel AMX dialect (architectural-specific vector dialect) 2021-03-15 17:59:05 -07:00