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llvm-project/llvm/lib/Target/Sparc
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Stanislav Mekhanoshin e98944ed47 Use bitset for assembler predicates 
AMDGPU target run out of Subtarget feature flags hitting the limit of 64.
AssemblerPredicates uses at most uint64_t for their representation.
At the same time CodeGen has exhausted this a long time ago and switched
to a FeatureBitset with the current limit of 192 bits.

This patch completes transition to the bitset for feature bits extending
it to asm matcher and MC code emitter.

Differential Revision: https://reviews.llvm.org/D59002

llvm-svn: 355839
 		2019-03-11 17:04:35 +00:00
..
AsmParser Use bitset for assembler predicates 2019-03-11 17:04:35 +00:00
Disassembler Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
InstPrinter Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
MCTargetDesc Use bitset for assembler predicates 2019-03-11 17:04:35 +00:00
TargetInfo Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
CMakeLists.txt Consistently sort add_subdirectory calls in lib/Target/*/CMakeLists.txt 2018-04-23 12:49:34 +00:00
DelaySlotFiller.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
LLVMBuild.txt Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
LeonFeatures.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
LeonPasses.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
LeonPasses.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
README.txt
…
Sparc.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
Sparc.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcAsmPrinter.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcCallingConv.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcFrameLowering.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcFrameLowering.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcISelDAGToDAG.cpp Implementation of asm-goto support in LLVM 2019-02-08 20:48:56 +00:00
SparcISelLowering.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcISelLowering.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcInstr64Bit.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcInstrAliases.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcInstrFormats.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcInstrInfo.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcInstrInfo.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcInstrInfo.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcInstrVIS.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcMCInstLower.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcMachineFunctionInfo.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcMachineFunctionInfo.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcRegisterInfo.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcRegisterInfo.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcRegisterInfo.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcSchedule.td Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcSubtarget.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcSubtarget.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcTargetMachine.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcTargetMachine.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcTargetObjectFile.cpp Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00
SparcTargetObjectFile.h Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00

README.txt 

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.