forked from OSchip/llvm-project
804 lines
35 KiB
TableGen
804 lines
35 KiB
TableGen
//===---- SMInstructions.td - Scalar Memory Instruction Defintions --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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def smrd_offset_8 : NamedOperandU32<"SMRDOffset8",
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NamedMatchClass<"SMRDOffset8">> {
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let OperandType = "OPERAND_IMMEDIATE";
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}
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def smrd_offset_20 : NamedOperandU32<"SMRDOffset20",
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NamedMatchClass<"SMRDOffset20">> {
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let OperandType = "OPERAND_IMMEDIATE";
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}
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//===----------------------------------------------------------------------===//
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// Scalar Memory classes
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//===----------------------------------------------------------------------===//
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class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
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InstSI <outs, ins, "", pattern>,
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SIMCInstr<opName, SIEncodingFamily.NONE> {
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let isPseudo = 1;
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let isCodeGenOnly = 1;
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let LGKM_CNT = 1;
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let SMRD = 1;
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let mayStore = 0;
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let mayLoad = 1;
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let hasSideEffects = 0;
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let UseNamedOperandTable = 1;
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let SchedRW = [WriteSMEM];
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string Mnemonic = opName;
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string AsmOperands = asmOps;
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bits<1> has_sbase = 1;
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bits<1> has_sdst = 1;
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bit has_glc = 0;
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bits<1> has_offset = 1;
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bits<1> offset_is_imm = 0;
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}
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class SM_Real <SM_Pseudo ps>
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: InstSI<ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
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let isPseudo = 0;
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let isCodeGenOnly = 0;
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// copy relevant pseudo op flags
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let SubtargetPredicate = ps.SubtargetPredicate;
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let AsmMatchConverter = ps.AsmMatchConverter;
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// encoding
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bits<7> sbase;
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bits<7> sdst;
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bits<32> offset;
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bits<1> imm = !if(ps.has_offset, ps.offset_is_imm, 0);
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}
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class SM_Probe_Pseudo <string opName, dag ins, bit isImm>
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: SM_Pseudo<opName, (outs), ins, " $sdata, $sbase, $offset"> {
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let mayLoad = 0;
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let mayStore = 0;
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let has_glc = 0;
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let LGKM_CNT = 0;
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let ScalarStore = 0;
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let hasSideEffects = 1;
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let offset_is_imm = isImm;
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let PseudoInstr = opName # !if(isImm, "_IMM", "_SGPR");
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}
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class SM_Load_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]>
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: SM_Pseudo<opName, outs, ins, asmOps, pattern> {
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RegisterClass BaseClass;
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let mayLoad = 1;
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let mayStore = 0;
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let has_glc = 1;
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}
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class SM_Store_Pseudo <string opName, dag ins, string asmOps, list<dag> pattern = []>
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: SM_Pseudo<opName, (outs), ins, asmOps, pattern> {
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RegisterClass BaseClass;
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RegisterClass SrcClass;
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let mayLoad = 0;
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let mayStore = 1;
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let has_glc = 1;
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let ScalarStore = 1;
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}
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class SM_Discard_Pseudo <string opName, dag ins, bit isImm>
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: SM_Pseudo<opName, (outs), ins, " $sbase, $offset"> {
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let mayLoad = 0;
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let mayStore = 0;
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let has_glc = 0;
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let has_sdst = 0;
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let ScalarStore = 0;
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let hasSideEffects = 1;
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let offset_is_imm = isImm;
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let PseudoInstr = opName # !if(isImm, "_IMM", "_SGPR");
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}
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multiclass SM_Pseudo_Loads<string opName,
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RegisterClass baseClass,
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RegisterClass dstClass> {
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def _IMM : SM_Load_Pseudo <opName,
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(outs dstClass:$sdst),
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(ins baseClass:$sbase, i32imm:$offset, i1imm:$glc),
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" $sdst, $sbase, $offset$glc", []> {
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let offset_is_imm = 1;
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let BaseClass = baseClass;
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let PseudoInstr = opName # "_IMM";
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let has_glc = 1;
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}
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def _SGPR : SM_Load_Pseudo <opName,
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(outs dstClass:$sdst),
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(ins baseClass:$sbase, SReg_32:$soff, i1imm:$glc),
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" $sdst, $sbase, $offset$glc", []> {
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let BaseClass = baseClass;
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let PseudoInstr = opName # "_SGPR";
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let has_glc = 1;
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}
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}
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multiclass SM_Pseudo_Stores<string opName,
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RegisterClass baseClass,
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RegisterClass srcClass> {
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def _IMM : SM_Store_Pseudo <opName,
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(ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, i1imm:$glc),
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" $sdata, $sbase, $offset$glc", []> {
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let offset_is_imm = 1;
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let BaseClass = baseClass;
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let SrcClass = srcClass;
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let PseudoInstr = opName # "_IMM";
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}
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def _SGPR : SM_Store_Pseudo <opName,
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(ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, i1imm:$glc),
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" $sdata, $sbase, $offset$glc", []> {
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let BaseClass = baseClass;
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let SrcClass = srcClass;
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let PseudoInstr = opName # "_SGPR";
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}
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}
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multiclass SM_Pseudo_Discards<string opName> {
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def _IMM : SM_Discard_Pseudo <opName, (ins SReg_64:$sbase, smrd_offset_20:$offset), 1>;
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def _SGPR : SM_Discard_Pseudo <opName, (ins SReg_64:$sbase, SReg_32:$offset), 0>;
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}
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class SM_Time_Pseudo<string opName, SDPatternOperator node = null_frag> : SM_Pseudo<
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opName, (outs SReg_64_XEXEC:$sdst), (ins),
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" $sdst", [(set i64:$sdst, (node))]> {
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let hasSideEffects = 1;
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// FIXME: This should be definitively mayStore = 0. TableGen
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// brokenly tries to infer these based on the intrinsic properties
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// corresponding to the IR attributes. The target intrinsics are
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// considered as writing to memory for IR dependency purposes, but
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// those can be modeled with hasSideEffects here. These also end up
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// inferring differently for llvm.readcyclecounter and the amdgcn
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// intrinsics.
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let mayStore = ?;
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let mayLoad = 1;
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let has_sbase = 0;
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let has_offset = 0;
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}
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class SM_Inval_Pseudo <string opName, SDPatternOperator node> : SM_Pseudo<
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opName, (outs), (ins), "", [(node)]> {
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let hasSideEffects = 1;
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let mayStore = 1;
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let has_sdst = 0;
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let has_sbase = 0;
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let has_offset = 0;
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}
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multiclass SM_Pseudo_Probe<string opName, RegisterClass baseClass> {
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def _IMM : SM_Probe_Pseudo <opName, (ins i8imm:$sdata, baseClass:$sbase, smrd_offset_20:$offset), 1>;
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def _SGPR : SM_Probe_Pseudo <opName, (ins i8imm:$sdata, baseClass:$sbase, SReg_32:$offset), 0>;
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}
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//===----------------------------------------------------------------------===//
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// Scalar Atomic Memory Classes
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//===----------------------------------------------------------------------===//
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class SM_Atomic_Pseudo <string opName,
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dag outs, dag ins, string asmOps, bit isRet>
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: SM_Pseudo<opName, outs, ins, asmOps, []> {
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bit glc = isRet;
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let mayLoad = 1;
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let mayStore = 1;
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let has_glc = 1;
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// Should these be set?
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let ScalarStore = 1;
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let hasSideEffects = 1;
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let maybeAtomic = 1;
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}
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class SM_Pseudo_Atomic<string opName,
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RegisterClass baseClass,
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RegisterClass dataClass,
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bit isImm,
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bit isRet> :
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SM_Atomic_Pseudo<opName,
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!if(isRet, (outs dataClass:$sdst), (outs)),
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!if(isImm,
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(ins dataClass:$sdata, baseClass:$sbase, smrd_offset_20:$offset),
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(ins dataClass:$sdata, baseClass:$sbase, SReg_32:$offset)),
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!if(isRet, " $sdst", " $sdata") # ", $sbase, $offset" # !if(isRet, " glc", ""),
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isRet> {
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let offset_is_imm = isImm;
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let PseudoInstr = opName # !if(isImm,
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!if(isRet, "_IMM_RTN", "_IMM"),
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!if(isRet, "_SGPR_RTN", "_SGPR"));
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let Constraints = !if(isRet, "$sdst = $sdata", "");
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let DisableEncoding = !if(isRet, "$sdata", "");
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}
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multiclass SM_Pseudo_Atomics<string opName,
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RegisterClass baseClass,
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RegisterClass dataClass> {
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def _IMM : SM_Pseudo_Atomic <opName, baseClass, dataClass, 1, 0>;
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def _SGPR : SM_Pseudo_Atomic <opName, baseClass, dataClass, 0, 0>;
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def _IMM_RTN : SM_Pseudo_Atomic <opName, baseClass, dataClass, 1, 1>;
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def _SGPR_RTN : SM_Pseudo_Atomic <opName, baseClass, dataClass, 0, 1>;
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}
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//===----------------------------------------------------------------------===//
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// Scalar Memory Instructions
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//===----------------------------------------------------------------------===//
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// We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
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// SMRD instructions, because the SReg_32_XM0 register class does not include M0
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// and writing to M0 from an SMRD instruction will hang the GPU.
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// XXX - SMEM instructions do not allow exec for data operand, but
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// does sdst for SMRD on SI/CI?
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defm S_LOAD_DWORD : SM_Pseudo_Loads <"s_load_dword", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_LOAD_DWORDX2 : SM_Pseudo_Loads <"s_load_dwordx2", SReg_64, SReg_64_XEXEC>;
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defm S_LOAD_DWORDX4 : SM_Pseudo_Loads <"s_load_dwordx4", SReg_64, SReg_128>;
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defm S_LOAD_DWORDX8 : SM_Pseudo_Loads <"s_load_dwordx8", SReg_64, SReg_256>;
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defm S_LOAD_DWORDX16 : SM_Pseudo_Loads <"s_load_dwordx16", SReg_64, SReg_512>;
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defm S_BUFFER_LOAD_DWORD : SM_Pseudo_Loads <
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"s_buffer_load_dword", SReg_128, SReg_32_XM0_XEXEC
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>;
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// FIXME: exec_lo/exec_hi appear to be allowed for SMRD loads on
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// SI/CI, bit disallowed for SMEM on VI.
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defm S_BUFFER_LOAD_DWORDX2 : SM_Pseudo_Loads <
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"s_buffer_load_dwordx2", SReg_128, SReg_64_XEXEC
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>;
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defm S_BUFFER_LOAD_DWORDX4 : SM_Pseudo_Loads <
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"s_buffer_load_dwordx4", SReg_128, SReg_128
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>;
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defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads <
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"s_buffer_load_dwordx8", SReg_128, SReg_256
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>;
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defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads <
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"s_buffer_load_dwordx16", SReg_128, SReg_512
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>;
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defm S_STORE_DWORD : SM_Pseudo_Stores <"s_store_dword", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_STORE_DWORDX2 : SM_Pseudo_Stores <"s_store_dwordx2", SReg_64, SReg_64_XEXEC>;
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defm S_STORE_DWORDX4 : SM_Pseudo_Stores <"s_store_dwordx4", SReg_64, SReg_128>;
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defm S_BUFFER_STORE_DWORD : SM_Pseudo_Stores <
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"s_buffer_store_dword", SReg_128, SReg_32_XM0_XEXEC
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>;
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defm S_BUFFER_STORE_DWORDX2 : SM_Pseudo_Stores <
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"s_buffer_store_dwordx2", SReg_128, SReg_64_XEXEC
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>;
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defm S_BUFFER_STORE_DWORDX4 : SM_Pseudo_Stores <
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"s_buffer_store_dwordx4", SReg_128, SReg_128
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>;
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def S_MEMTIME : SM_Time_Pseudo <"s_memtime", int_amdgcn_s_memtime>;
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def S_DCACHE_INV : SM_Inval_Pseudo <"s_dcache_inv", int_amdgcn_s_dcache_inv>;
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let SubtargetPredicate = isCIVI in {
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def S_DCACHE_INV_VOL : SM_Inval_Pseudo <"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
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} // let SubtargetPredicate = isCIVI
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let SubtargetPredicate = isVI in {
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def S_DCACHE_WB : SM_Inval_Pseudo <"s_dcache_wb", int_amdgcn_s_dcache_wb>;
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def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
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def S_MEMREALTIME : SM_Time_Pseudo <"s_memrealtime", int_amdgcn_s_memrealtime>;
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defm S_ATC_PROBE : SM_Pseudo_Probe <"s_atc_probe", SReg_64>;
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defm S_ATC_PROBE_BUFFER : SM_Pseudo_Probe <"s_atc_probe_buffer", SReg_128>;
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} // SubtargetPredicate = isVI
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let SubtargetPredicate = HasFlatScratchInsts, Uses = [FLAT_SCR] in {
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defm S_SCRATCH_LOAD_DWORD : SM_Pseudo_Loads <"s_scratch_load_dword", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_SCRATCH_LOAD_DWORDX2 : SM_Pseudo_Loads <"s_scratch_load_dwordx2", SReg_64, SReg_64_XEXEC>;
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defm S_SCRATCH_LOAD_DWORDX4 : SM_Pseudo_Loads <"s_scratch_load_dwordx4", SReg_64, SReg_128>;
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defm S_SCRATCH_STORE_DWORD : SM_Pseudo_Stores <"s_scratch_store_dword", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_SCRATCH_STORE_DWORDX2 : SM_Pseudo_Stores <"s_scratch_store_dwordx2", SReg_64, SReg_64_XEXEC>;
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defm S_SCRATCH_STORE_DWORDX4 : SM_Pseudo_Stores <"s_scratch_store_dwordx4", SReg_64, SReg_128>;
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} // SubtargetPredicate = HasFlatScratchInsts
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let SubtargetPredicate = HasScalarAtomics in {
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defm S_BUFFER_ATOMIC_SWAP : SM_Pseudo_Atomics <"s_buffer_atomic_swap", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_BUFFER_ATOMIC_CMPSWAP : SM_Pseudo_Atomics <"s_buffer_atomic_cmpswap", SReg_128, SReg_64_XEXEC>;
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defm S_BUFFER_ATOMIC_ADD : SM_Pseudo_Atomics <"s_buffer_atomic_add", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_BUFFER_ATOMIC_SUB : SM_Pseudo_Atomics <"s_buffer_atomic_sub", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_BUFFER_ATOMIC_SMIN : SM_Pseudo_Atomics <"s_buffer_atomic_smin", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_BUFFER_ATOMIC_UMIN : SM_Pseudo_Atomics <"s_buffer_atomic_umin", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_BUFFER_ATOMIC_SMAX : SM_Pseudo_Atomics <"s_buffer_atomic_smax", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_BUFFER_ATOMIC_UMAX : SM_Pseudo_Atomics <"s_buffer_atomic_umax", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_BUFFER_ATOMIC_AND : SM_Pseudo_Atomics <"s_buffer_atomic_and", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_BUFFER_ATOMIC_OR : SM_Pseudo_Atomics <"s_buffer_atomic_or", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_BUFFER_ATOMIC_XOR : SM_Pseudo_Atomics <"s_buffer_atomic_xor", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_BUFFER_ATOMIC_INC : SM_Pseudo_Atomics <"s_buffer_atomic_inc", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_BUFFER_ATOMIC_DEC : SM_Pseudo_Atomics <"s_buffer_atomic_dec", SReg_128, SReg_32_XM0_XEXEC>;
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defm S_BUFFER_ATOMIC_SWAP_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_swap_x2", SReg_128, SReg_64_XEXEC>;
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defm S_BUFFER_ATOMIC_CMPSWAP_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_cmpswap_x2", SReg_128, SReg_128>;
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defm S_BUFFER_ATOMIC_ADD_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_add_x2", SReg_128, SReg_64_XEXEC>;
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defm S_BUFFER_ATOMIC_SUB_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_sub_x2", SReg_128, SReg_64_XEXEC>;
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defm S_BUFFER_ATOMIC_SMIN_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_smin_x2", SReg_128, SReg_64_XEXEC>;
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defm S_BUFFER_ATOMIC_UMIN_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_umin_x2", SReg_128, SReg_64_XEXEC>;
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defm S_BUFFER_ATOMIC_SMAX_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_smax_x2", SReg_128, SReg_64_XEXEC>;
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defm S_BUFFER_ATOMIC_UMAX_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_umax_x2", SReg_128, SReg_64_XEXEC>;
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defm S_BUFFER_ATOMIC_AND_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_and_x2", SReg_128, SReg_64_XEXEC>;
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defm S_BUFFER_ATOMIC_OR_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_or_x2", SReg_128, SReg_64_XEXEC>;
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defm S_BUFFER_ATOMIC_XOR_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_xor_x2", SReg_128, SReg_64_XEXEC>;
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defm S_BUFFER_ATOMIC_INC_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_inc_x2", SReg_128, SReg_64_XEXEC>;
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defm S_BUFFER_ATOMIC_DEC_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_dec_x2", SReg_128, SReg_64_XEXEC>;
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defm S_ATOMIC_SWAP : SM_Pseudo_Atomics <"s_atomic_swap", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_ATOMIC_CMPSWAP : SM_Pseudo_Atomics <"s_atomic_cmpswap", SReg_64, SReg_64_XEXEC>;
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defm S_ATOMIC_ADD : SM_Pseudo_Atomics <"s_atomic_add", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_ATOMIC_SUB : SM_Pseudo_Atomics <"s_atomic_sub", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_ATOMIC_SMIN : SM_Pseudo_Atomics <"s_atomic_smin", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_ATOMIC_UMIN : SM_Pseudo_Atomics <"s_atomic_umin", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_ATOMIC_SMAX : SM_Pseudo_Atomics <"s_atomic_smax", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_ATOMIC_UMAX : SM_Pseudo_Atomics <"s_atomic_umax", SReg_64, SReg_32_XM0_XEXEC>;
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defm S_ATOMIC_AND : SM_Pseudo_Atomics <"s_atomic_and", SReg_64, SReg_32_XM0_XEXEC>;
|
|
defm S_ATOMIC_OR : SM_Pseudo_Atomics <"s_atomic_or", SReg_64, SReg_32_XM0_XEXEC>;
|
|
defm S_ATOMIC_XOR : SM_Pseudo_Atomics <"s_atomic_xor", SReg_64, SReg_32_XM0_XEXEC>;
|
|
defm S_ATOMIC_INC : SM_Pseudo_Atomics <"s_atomic_inc", SReg_64, SReg_32_XM0_XEXEC>;
|
|
defm S_ATOMIC_DEC : SM_Pseudo_Atomics <"s_atomic_dec", SReg_64, SReg_32_XM0_XEXEC>;
|
|
|
|
defm S_ATOMIC_SWAP_X2 : SM_Pseudo_Atomics <"s_atomic_swap_x2", SReg_64, SReg_64_XEXEC>;
|
|
defm S_ATOMIC_CMPSWAP_X2 : SM_Pseudo_Atomics <"s_atomic_cmpswap_x2", SReg_64, SReg_128>;
|
|
defm S_ATOMIC_ADD_X2 : SM_Pseudo_Atomics <"s_atomic_add_x2", SReg_64, SReg_64_XEXEC>;
|
|
defm S_ATOMIC_SUB_X2 : SM_Pseudo_Atomics <"s_atomic_sub_x2", SReg_64, SReg_64_XEXEC>;
|
|
defm S_ATOMIC_SMIN_X2 : SM_Pseudo_Atomics <"s_atomic_smin_x2", SReg_64, SReg_64_XEXEC>;
|
|
defm S_ATOMIC_UMIN_X2 : SM_Pseudo_Atomics <"s_atomic_umin_x2", SReg_64, SReg_64_XEXEC>;
|
|
defm S_ATOMIC_SMAX_X2 : SM_Pseudo_Atomics <"s_atomic_smax_x2", SReg_64, SReg_64_XEXEC>;
|
|
defm S_ATOMIC_UMAX_X2 : SM_Pseudo_Atomics <"s_atomic_umax_x2", SReg_64, SReg_64_XEXEC>;
|
|
defm S_ATOMIC_AND_X2 : SM_Pseudo_Atomics <"s_atomic_and_x2", SReg_64, SReg_64_XEXEC>;
|
|
defm S_ATOMIC_OR_X2 : SM_Pseudo_Atomics <"s_atomic_or_x2", SReg_64, SReg_64_XEXEC>;
|
|
defm S_ATOMIC_XOR_X2 : SM_Pseudo_Atomics <"s_atomic_xor_x2", SReg_64, SReg_64_XEXEC>;
|
|
defm S_ATOMIC_INC_X2 : SM_Pseudo_Atomics <"s_atomic_inc_x2", SReg_64, SReg_64_XEXEC>;
|
|
defm S_ATOMIC_DEC_X2 : SM_Pseudo_Atomics <"s_atomic_dec_x2", SReg_64, SReg_64_XEXEC>;
|
|
|
|
} // let SubtargetPredicate = HasScalarAtomics
|
|
|
|
let SubtargetPredicate = isGFX9 in {
|
|
defm S_DCACHE_DISCARD : SM_Pseudo_Discards <"s_dcache_discard">;
|
|
defm S_DCACHE_DISCARD_X2 : SM_Pseudo_Discards <"s_dcache_discard_x2">;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Targets
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SI
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class SMRD_Real_si <bits<5> op, SM_Pseudo ps>
|
|
: SM_Real<ps>
|
|
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
|
|
, Enc32 {
|
|
|
|
let AssemblerPredicates = [isSICI];
|
|
let DecoderNamespace = "SICI";
|
|
|
|
let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
|
|
let Inst{8} = imm;
|
|
let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
|
|
let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
|
|
let Inst{26-22} = op;
|
|
let Inst{31-27} = 0x18; //encoding
|
|
}
|
|
|
|
// FIXME: Assembler should reject trying to use glc on SMRD
|
|
// instructions on SI.
|
|
multiclass SM_Real_Loads_si<bits<5> op, string ps,
|
|
SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
|
|
SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
|
|
|
|
def _IMM_si : SMRD_Real_si <op, immPs> {
|
|
let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, GLC:$glc);
|
|
}
|
|
|
|
// FIXME: The operand name $offset is inconsistent with $soff used
|
|
// in the pseudo
|
|
def _SGPR_si : SMRD_Real_si <op, sgprPs> {
|
|
let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
|
|
}
|
|
|
|
}
|
|
|
|
defm S_LOAD_DWORD : SM_Real_Loads_si <0x00, "S_LOAD_DWORD">;
|
|
defm S_LOAD_DWORDX2 : SM_Real_Loads_si <0x01, "S_LOAD_DWORDX2">;
|
|
defm S_LOAD_DWORDX4 : SM_Real_Loads_si <0x02, "S_LOAD_DWORDX4">;
|
|
defm S_LOAD_DWORDX8 : SM_Real_Loads_si <0x03, "S_LOAD_DWORDX8">;
|
|
defm S_LOAD_DWORDX16 : SM_Real_Loads_si <0x04, "S_LOAD_DWORDX16">;
|
|
defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_si <0x08, "S_BUFFER_LOAD_DWORD">;
|
|
defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_si <0x09, "S_BUFFER_LOAD_DWORDX2">;
|
|
defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_si <0x0a, "S_BUFFER_LOAD_DWORDX4">;
|
|
defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_si <0x0b, "S_BUFFER_LOAD_DWORDX8">;
|
|
defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_si <0x0c, "S_BUFFER_LOAD_DWORDX16">;
|
|
|
|
def S_MEMTIME_si : SMRD_Real_si <0x1e, S_MEMTIME>;
|
|
def S_DCACHE_INV_si : SMRD_Real_si <0x1f, S_DCACHE_INV>;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// VI
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
|
|
: SM_Real<ps>
|
|
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
|
|
, Enc64 {
|
|
bit glc;
|
|
|
|
let AssemblerPredicates = [isVI];
|
|
let DecoderNamespace = "VI";
|
|
|
|
let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
|
|
let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
|
|
|
|
let Inst{16} = !if(ps.has_glc, glc, ?);
|
|
let Inst{17} = imm;
|
|
let Inst{25-18} = op;
|
|
let Inst{31-26} = 0x30; //encoding
|
|
let Inst{51-32} = !if(ps.has_offset, offset{19-0}, ?);
|
|
}
|
|
|
|
multiclass SM_Real_Loads_vi<bits<8> op, string ps,
|
|
SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
|
|
SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
|
|
def _IMM_vi : SMEM_Real_vi <op, immPs> {
|
|
let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc);
|
|
}
|
|
def _SGPR_vi : SMEM_Real_vi <op, sgprPs> {
|
|
let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
|
|
}
|
|
}
|
|
|
|
class SMEM_Real_Store_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
|
|
// encoding
|
|
bits<7> sdata;
|
|
|
|
let sdst = ?;
|
|
let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
|
|
}
|
|
|
|
multiclass SM_Real_Stores_vi<bits<8> op, string ps,
|
|
SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM),
|
|
SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> {
|
|
// FIXME: The operand name $offset is inconsistent with $soff used
|
|
// in the pseudo
|
|
def _IMM_vi : SMEM_Real_Store_vi <op, immPs> {
|
|
let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc);
|
|
}
|
|
|
|
def _SGPR_vi : SMEM_Real_Store_vi <op, sgprPs> {
|
|
let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
|
|
}
|
|
}
|
|
|
|
multiclass SM_Real_Probe_vi<bits<8> op, string ps> {
|
|
def _IMM_vi : SMEM_Real_Store_vi <op, !cast<SM_Probe_Pseudo>(ps#_IMM)>;
|
|
def _SGPR_vi : SMEM_Real_Store_vi <op, !cast<SM_Probe_Pseudo>(ps#_SGPR)>;
|
|
}
|
|
|
|
defm S_LOAD_DWORD : SM_Real_Loads_vi <0x00, "S_LOAD_DWORD">;
|
|
defm S_LOAD_DWORDX2 : SM_Real_Loads_vi <0x01, "S_LOAD_DWORDX2">;
|
|
defm S_LOAD_DWORDX4 : SM_Real_Loads_vi <0x02, "S_LOAD_DWORDX4">;
|
|
defm S_LOAD_DWORDX8 : SM_Real_Loads_vi <0x03, "S_LOAD_DWORDX8">;
|
|
defm S_LOAD_DWORDX16 : SM_Real_Loads_vi <0x04, "S_LOAD_DWORDX16">;
|
|
defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_vi <0x08, "S_BUFFER_LOAD_DWORD">;
|
|
defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_vi <0x09, "S_BUFFER_LOAD_DWORDX2">;
|
|
defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_vi <0x0a, "S_BUFFER_LOAD_DWORDX4">;
|
|
defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_vi <0x0b, "S_BUFFER_LOAD_DWORDX8">;
|
|
defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_vi <0x0c, "S_BUFFER_LOAD_DWORDX16">;
|
|
|
|
defm S_STORE_DWORD : SM_Real_Stores_vi <0x10, "S_STORE_DWORD">;
|
|
defm S_STORE_DWORDX2 : SM_Real_Stores_vi <0x11, "S_STORE_DWORDX2">;
|
|
defm S_STORE_DWORDX4 : SM_Real_Stores_vi <0x12, "S_STORE_DWORDX4">;
|
|
|
|
defm S_BUFFER_STORE_DWORD : SM_Real_Stores_vi <0x18, "S_BUFFER_STORE_DWORD">;
|
|
defm S_BUFFER_STORE_DWORDX2 : SM_Real_Stores_vi <0x19, "S_BUFFER_STORE_DWORDX2">;
|
|
defm S_BUFFER_STORE_DWORDX4 : SM_Real_Stores_vi <0x1a, "S_BUFFER_STORE_DWORDX4">;
|
|
|
|
// These instructions use same encoding
|
|
def S_DCACHE_INV_vi : SMEM_Real_vi <0x20, S_DCACHE_INV>;
|
|
def S_DCACHE_WB_vi : SMEM_Real_vi <0x21, S_DCACHE_WB>;
|
|
def S_DCACHE_INV_VOL_vi : SMEM_Real_vi <0x22, S_DCACHE_INV_VOL>;
|
|
def S_DCACHE_WB_VOL_vi : SMEM_Real_vi <0x23, S_DCACHE_WB_VOL>;
|
|
def S_MEMTIME_vi : SMEM_Real_vi <0x24, S_MEMTIME>;
|
|
def S_MEMREALTIME_vi : SMEM_Real_vi <0x25, S_MEMREALTIME>;
|
|
|
|
defm S_SCRATCH_LOAD_DWORD : SM_Real_Loads_vi <0x05, "S_SCRATCH_LOAD_DWORD">;
|
|
defm S_SCRATCH_LOAD_DWORDX2 : SM_Real_Loads_vi <0x06, "S_SCRATCH_LOAD_DWORDX2">;
|
|
defm S_SCRATCH_LOAD_DWORDX4 : SM_Real_Loads_vi <0x07, "S_SCRATCH_LOAD_DWORDX4">;
|
|
|
|
defm S_SCRATCH_STORE_DWORD : SM_Real_Stores_vi <0x15, "S_SCRATCH_STORE_DWORD">;
|
|
defm S_SCRATCH_STORE_DWORDX2 : SM_Real_Stores_vi <0x16, "S_SCRATCH_STORE_DWORDX2">;
|
|
defm S_SCRATCH_STORE_DWORDX4 : SM_Real_Stores_vi <0x17, "S_SCRATCH_STORE_DWORDX4">;
|
|
|
|
defm S_ATC_PROBE : SM_Real_Probe_vi <0x26, "S_ATC_PROBE">;
|
|
defm S_ATC_PROBE_BUFFER : SM_Real_Probe_vi <0x27, "S_ATC_PROBE_BUFFER">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// GFX9
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class SMEM_Atomic_Real_vi <bits<8> op, SM_Atomic_Pseudo ps>
|
|
: SMEM_Real_vi <op, ps> {
|
|
|
|
bits<7> sdata;
|
|
|
|
let Constraints = ps.Constraints;
|
|
let DisableEncoding = ps.DisableEncoding;
|
|
|
|
let glc = ps.glc;
|
|
let Inst{12-6} = !if(glc, sdst{6-0}, sdata{6-0});
|
|
}
|
|
|
|
multiclass SM_Real_Atomics_vi<bits<8> op, string ps> {
|
|
def _IMM_vi : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_IMM)>;
|
|
def _SGPR_vi : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR)>;
|
|
def _IMM_RTN_vi : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_IMM_RTN)>;
|
|
def _SGPR_RTN_vi : SMEM_Atomic_Real_vi <op, !cast<SM_Atomic_Pseudo>(ps#_SGPR_RTN)>;
|
|
}
|
|
|
|
defm S_BUFFER_ATOMIC_SWAP : SM_Real_Atomics_vi <0x40, "S_BUFFER_ATOMIC_SWAP">;
|
|
defm S_BUFFER_ATOMIC_CMPSWAP : SM_Real_Atomics_vi <0x41, "S_BUFFER_ATOMIC_CMPSWAP">;
|
|
defm S_BUFFER_ATOMIC_ADD : SM_Real_Atomics_vi <0x42, "S_BUFFER_ATOMIC_ADD">;
|
|
defm S_BUFFER_ATOMIC_SUB : SM_Real_Atomics_vi <0x43, "S_BUFFER_ATOMIC_SUB">;
|
|
defm S_BUFFER_ATOMIC_SMIN : SM_Real_Atomics_vi <0x44, "S_BUFFER_ATOMIC_SMIN">;
|
|
defm S_BUFFER_ATOMIC_UMIN : SM_Real_Atomics_vi <0x45, "S_BUFFER_ATOMIC_UMIN">;
|
|
defm S_BUFFER_ATOMIC_SMAX : SM_Real_Atomics_vi <0x46, "S_BUFFER_ATOMIC_SMAX">;
|
|
defm S_BUFFER_ATOMIC_UMAX : SM_Real_Atomics_vi <0x47, "S_BUFFER_ATOMIC_UMAX">;
|
|
defm S_BUFFER_ATOMIC_AND : SM_Real_Atomics_vi <0x48, "S_BUFFER_ATOMIC_AND">;
|
|
defm S_BUFFER_ATOMIC_OR : SM_Real_Atomics_vi <0x49, "S_BUFFER_ATOMIC_OR">;
|
|
defm S_BUFFER_ATOMIC_XOR : SM_Real_Atomics_vi <0x4a, "S_BUFFER_ATOMIC_XOR">;
|
|
defm S_BUFFER_ATOMIC_INC : SM_Real_Atomics_vi <0x4b, "S_BUFFER_ATOMIC_INC">;
|
|
defm S_BUFFER_ATOMIC_DEC : SM_Real_Atomics_vi <0x4c, "S_BUFFER_ATOMIC_DEC">;
|
|
|
|
defm S_BUFFER_ATOMIC_SWAP_X2 : SM_Real_Atomics_vi <0x60, "S_BUFFER_ATOMIC_SWAP_X2">;
|
|
defm S_BUFFER_ATOMIC_CMPSWAP_X2 : SM_Real_Atomics_vi <0x61, "S_BUFFER_ATOMIC_CMPSWAP_X2">;
|
|
defm S_BUFFER_ATOMIC_ADD_X2 : SM_Real_Atomics_vi <0x62, "S_BUFFER_ATOMIC_ADD_X2">;
|
|
defm S_BUFFER_ATOMIC_SUB_X2 : SM_Real_Atomics_vi <0x63, "S_BUFFER_ATOMIC_SUB_X2">;
|
|
defm S_BUFFER_ATOMIC_SMIN_X2 : SM_Real_Atomics_vi <0x64, "S_BUFFER_ATOMIC_SMIN_X2">;
|
|
defm S_BUFFER_ATOMIC_UMIN_X2 : SM_Real_Atomics_vi <0x65, "S_BUFFER_ATOMIC_UMIN_X2">;
|
|
defm S_BUFFER_ATOMIC_SMAX_X2 : SM_Real_Atomics_vi <0x66, "S_BUFFER_ATOMIC_SMAX_X2">;
|
|
defm S_BUFFER_ATOMIC_UMAX_X2 : SM_Real_Atomics_vi <0x67, "S_BUFFER_ATOMIC_UMAX_X2">;
|
|
defm S_BUFFER_ATOMIC_AND_X2 : SM_Real_Atomics_vi <0x68, "S_BUFFER_ATOMIC_AND_X2">;
|
|
defm S_BUFFER_ATOMIC_OR_X2 : SM_Real_Atomics_vi <0x69, "S_BUFFER_ATOMIC_OR_X2">;
|
|
defm S_BUFFER_ATOMIC_XOR_X2 : SM_Real_Atomics_vi <0x6a, "S_BUFFER_ATOMIC_XOR_X2">;
|
|
defm S_BUFFER_ATOMIC_INC_X2 : SM_Real_Atomics_vi <0x6b, "S_BUFFER_ATOMIC_INC_X2">;
|
|
defm S_BUFFER_ATOMIC_DEC_X2 : SM_Real_Atomics_vi <0x6c, "S_BUFFER_ATOMIC_DEC_X2">;
|
|
|
|
defm S_ATOMIC_SWAP : SM_Real_Atomics_vi <0x80, "S_ATOMIC_SWAP">;
|
|
defm S_ATOMIC_CMPSWAP : SM_Real_Atomics_vi <0x81, "S_ATOMIC_CMPSWAP">;
|
|
defm S_ATOMIC_ADD : SM_Real_Atomics_vi <0x82, "S_ATOMIC_ADD">;
|
|
defm S_ATOMIC_SUB : SM_Real_Atomics_vi <0x83, "S_ATOMIC_SUB">;
|
|
defm S_ATOMIC_SMIN : SM_Real_Atomics_vi <0x84, "S_ATOMIC_SMIN">;
|
|
defm S_ATOMIC_UMIN : SM_Real_Atomics_vi <0x85, "S_ATOMIC_UMIN">;
|
|
defm S_ATOMIC_SMAX : SM_Real_Atomics_vi <0x86, "S_ATOMIC_SMAX">;
|
|
defm S_ATOMIC_UMAX : SM_Real_Atomics_vi <0x87, "S_ATOMIC_UMAX">;
|
|
defm S_ATOMIC_AND : SM_Real_Atomics_vi <0x88, "S_ATOMIC_AND">;
|
|
defm S_ATOMIC_OR : SM_Real_Atomics_vi <0x89, "S_ATOMIC_OR">;
|
|
defm S_ATOMIC_XOR : SM_Real_Atomics_vi <0x8a, "S_ATOMIC_XOR">;
|
|
defm S_ATOMIC_INC : SM_Real_Atomics_vi <0x8b, "S_ATOMIC_INC">;
|
|
defm S_ATOMIC_DEC : SM_Real_Atomics_vi <0x8c, "S_ATOMIC_DEC">;
|
|
|
|
defm S_ATOMIC_SWAP_X2 : SM_Real_Atomics_vi <0xa0, "S_ATOMIC_SWAP_X2">;
|
|
defm S_ATOMIC_CMPSWAP_X2 : SM_Real_Atomics_vi <0xa1, "S_ATOMIC_CMPSWAP_X2">;
|
|
defm S_ATOMIC_ADD_X2 : SM_Real_Atomics_vi <0xa2, "S_ATOMIC_ADD_X2">;
|
|
defm S_ATOMIC_SUB_X2 : SM_Real_Atomics_vi <0xa3, "S_ATOMIC_SUB_X2">;
|
|
defm S_ATOMIC_SMIN_X2 : SM_Real_Atomics_vi <0xa4, "S_ATOMIC_SMIN_X2">;
|
|
defm S_ATOMIC_UMIN_X2 : SM_Real_Atomics_vi <0xa5, "S_ATOMIC_UMIN_X2">;
|
|
defm S_ATOMIC_SMAX_X2 : SM_Real_Atomics_vi <0xa6, "S_ATOMIC_SMAX_X2">;
|
|
defm S_ATOMIC_UMAX_X2 : SM_Real_Atomics_vi <0xa7, "S_ATOMIC_UMAX_X2">;
|
|
defm S_ATOMIC_AND_X2 : SM_Real_Atomics_vi <0xa8, "S_ATOMIC_AND_X2">;
|
|
defm S_ATOMIC_OR_X2 : SM_Real_Atomics_vi <0xa9, "S_ATOMIC_OR_X2">;
|
|
defm S_ATOMIC_XOR_X2 : SM_Real_Atomics_vi <0xaa, "S_ATOMIC_XOR_X2">;
|
|
defm S_ATOMIC_INC_X2 : SM_Real_Atomics_vi <0xab, "S_ATOMIC_INC_X2">;
|
|
defm S_ATOMIC_DEC_X2 : SM_Real_Atomics_vi <0xac, "S_ATOMIC_DEC_X2">;
|
|
|
|
multiclass SM_Real_Discard_vi<bits<8> op, string ps> {
|
|
def _IMM_vi : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_IMM)>;
|
|
def _SGPR_vi : SMEM_Real_vi <op, !cast<SM_Discard_Pseudo>(ps#_SGPR)>;
|
|
}
|
|
|
|
defm S_DCACHE_DISCARD : SM_Real_Discard_vi <0x28, "S_DCACHE_DISCARD">;
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defm S_DCACHE_DISCARD_X2 : SM_Real_Discard_vi <0x29, "S_DCACHE_DISCARD_X2">;
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//===----------------------------------------------------------------------===//
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// CI
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//===----------------------------------------------------------------------===//
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def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset",
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NamedMatchClass<"SMRDLiteralOffset">> {
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let OperandType = "OPERAND_IMMEDIATE";
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}
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class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
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SM_Real<ps>,
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Enc64 {
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let AssemblerPredicates = [isCIOnly];
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let DecoderNamespace = "CI";
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let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc);
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let LGKM_CNT = ps.LGKM_CNT;
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let SMRD = ps.SMRD;
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let mayLoad = ps.mayLoad;
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let mayStore = ps.mayStore;
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let hasSideEffects = ps.hasSideEffects;
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let SchedRW = ps.SchedRW;
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let UseNamedOperandTable = ps.UseNamedOperandTable;
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let Inst{7-0} = 0xff;
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let Inst{8} = 0;
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let Inst{14-9} = sbase{6-1};
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let Inst{21-15} = sdst{6-0};
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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let Inst{63-32} = offset{31-0};
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}
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def S_LOAD_DWORD_IMM_ci : SMRD_Real_Load_IMM_ci <0x00, S_LOAD_DWORD_IMM>;
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def S_LOAD_DWORDX2_IMM_ci : SMRD_Real_Load_IMM_ci <0x01, S_LOAD_DWORDX2_IMM>;
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def S_LOAD_DWORDX4_IMM_ci : SMRD_Real_Load_IMM_ci <0x02, S_LOAD_DWORDX4_IMM>;
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def S_LOAD_DWORDX8_IMM_ci : SMRD_Real_Load_IMM_ci <0x03, S_LOAD_DWORDX8_IMM>;
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def S_LOAD_DWORDX16_IMM_ci : SMRD_Real_Load_IMM_ci <0x04, S_LOAD_DWORDX16_IMM>;
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def S_BUFFER_LOAD_DWORD_IMM_ci : SMRD_Real_Load_IMM_ci <0x08, S_BUFFER_LOAD_DWORD_IMM>;
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def S_BUFFER_LOAD_DWORDX2_IMM_ci : SMRD_Real_Load_IMM_ci <0x09, S_BUFFER_LOAD_DWORDX2_IMM>;
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def S_BUFFER_LOAD_DWORDX4_IMM_ci : SMRD_Real_Load_IMM_ci <0x0a, S_BUFFER_LOAD_DWORDX4_IMM>;
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def S_BUFFER_LOAD_DWORDX8_IMM_ci : SMRD_Real_Load_IMM_ci <0x0b, S_BUFFER_LOAD_DWORDX8_IMM>;
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def S_BUFFER_LOAD_DWORDX16_IMM_ci : SMRD_Real_Load_IMM_ci <0x0c, S_BUFFER_LOAD_DWORDX16_IMM>;
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class SMRD_Real_ci <bits<5> op, SM_Pseudo ps>
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: SM_Real<ps>
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, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
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, Enc32 {
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let AssemblerPredicates = [isCIOnly];
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let DecoderNamespace = "CI";
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let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
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let Inst{8} = imm;
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let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
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let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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}
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def S_DCACHE_INV_VOL_ci : SMRD_Real_ci <0x1d, S_DCACHE_INV_VOL>;
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//===----------------------------------------------------------------------===//
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// Scalar Memory Patterns
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//===----------------------------------------------------------------------===//
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def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{ return isUniformLoad(N);}]> {
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let GISelPredicateCode = [{
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if (!MI.hasOneMemOperand())
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return false;
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if (!isInstrUniform(MI))
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return false;
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// FIXME: We should probably be caching this.
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SmallVector<GEPInfo, 4> AddrInfo;
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getAddrModeInfo(MI, MRI, AddrInfo);
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if (hasVgprParts(AddrInfo))
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return false;
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return true;
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}];
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}
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def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
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def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
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def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
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def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
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def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
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multiclass SMRD_Pattern <string Instr, ValueType vt> {
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// 1. IMM offset
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def : GCNPat <
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(smrd_load (SMRDImm i64:$sbase, i32:$offset)),
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(vt (!cast<SM_Pseudo>(Instr#"_IMM") $sbase, $offset, 0))
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>;
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// 2. 32-bit IMM offset on CI
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def : GCNPat <
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(smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
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(vt (!cast<InstSI>(Instr#"_IMM_ci") $sbase, $offset, 0))> {
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let OtherPredicates = [isCIOnly];
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}
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// 3. SGPR offset
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def : GCNPat <
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(smrd_load (SMRDSgpr i64:$sbase, i32:$offset)),
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(vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset, 0))
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>;
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// 4. No offset
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def : GCNPat <
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(vt (smrd_load (i64 SReg_64:$sbase))),
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(vt (!cast<SM_Pseudo>(Instr#"_IMM") i64:$sbase, 0, 0))
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>;
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}
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multiclass SMLoad_Pattern <string Instr, ValueType vt> {
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// 1. Offset as an immediate
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def : GCNPat <
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(SIsbuffer_load v4i32:$sbase, (SMRDBufferImm i32:$offset), i1:$glc),
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(vt (!cast<SM_Pseudo>(Instr#"_IMM") $sbase, $offset, (as_i1imm $glc)))
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>;
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// 2. 32-bit IMM offset on CI
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def : GCNPat <
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(vt (SIsbuffer_load v4i32:$sbase, (SMRDBufferImm32 i32:$offset), i1:$glc)),
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(!cast<InstSI>(Instr#"_IMM_ci") $sbase, $offset, (as_i1imm $glc))> {
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let OtherPredicates = [isCIOnly];
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}
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// 3. Offset loaded in an 32bit SGPR
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def : GCNPat <
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(SIsbuffer_load v4i32:$sbase, i32:$offset, i1:$glc),
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(vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset, (as_i1imm $glc)))
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>;
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}
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// Global and constant loads can be selected to either MUBUF or SMRD
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// instructions, but SMRD instructions are faster so we want the instruction
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// selector to prefer those.
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let AddedComplexity = 100 in {
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defm : SMRD_Pattern <"S_LOAD_DWORD", i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
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defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
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defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORD", i32>;
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defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX2", v2i32>;
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defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX4", v4i32>;
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defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX8", v8i32>;
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defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX16", v16i32>;
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defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORD", f32>;
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defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX2", v2f32>;
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defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX4", v4f32>;
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defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX8", v8f32>;
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defm : SMLoad_Pattern <"S_BUFFER_LOAD_DWORDX16", v16f32>;
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} // End let AddedComplexity = 100
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let OtherPredicates = [isSICI] in {
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def : GCNPat <
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(i64 (readcyclecounter)),
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(S_MEMTIME)
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>;
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}
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let OtherPredicates = [isVI] in {
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def : GCNPat <
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(i64 (readcyclecounter)),
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(S_MEMREALTIME)
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>;
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} // let OtherPredicates = [isVI]
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