forked from OSchip/llvm-project
205 lines
7.4 KiB
C++
205 lines
7.4 KiB
C++
//===-- WebAssemblyStoreResults.cpp - Optimize using store result values --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file implements an optimization pass using store result values.
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///
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/// WebAssembly's store instructions return the stored value. This is to enable
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/// an optimization wherein uses of the stored value can be replaced by uses of
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/// the store's result value, making the stored value register more likely to
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/// be single-use, thus more likely to be useful to register stackifying, and
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/// potentially also exposing the store to register stackifying. These both can
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/// reduce get_local/set_local traffic.
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///
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/// This pass also performs this optimization for memcpy, memmove, and memset
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/// calls, since the LLVM intrinsics for these return void so they can't use the
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/// returned attribute and consequently aren't handled by the OptimizeReturned
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/// pass.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssembly.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/Analysis/TargetLibraryInfo.h"
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#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-store-results"
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namespace {
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class WebAssemblyStoreResults final : public MachineFunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyStoreResults() : MachineFunctionPass(ID) {}
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const char *getPassName() const override {
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return "WebAssembly Store Results";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<MachineBlockFrequencyInfo>();
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AU.addPreserved<MachineBlockFrequencyInfo>();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<TargetLibraryInfoWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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};
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} // end anonymous namespace
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char WebAssemblyStoreResults::ID = 0;
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FunctionPass *llvm::createWebAssemblyStoreResults() {
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return new WebAssemblyStoreResults();
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}
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// Replace uses of FromReg with ToReg if they are dominated by MI.
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static bool ReplaceDominatedUses(MachineBasicBlock &MBB, MachineInstr &MI,
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unsigned FromReg, unsigned ToReg,
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const MachineRegisterInfo &MRI,
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MachineDominatorTree &MDT) {
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bool Changed = false;
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for (auto I = MRI.use_begin(FromReg), E = MRI.use_end(); I != E;) {
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MachineOperand &O = *I++;
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MachineInstr *Where = O.getParent();
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if (Where->getOpcode() == TargetOpcode::PHI) {
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// PHIs use their operands on their incoming CFG edges rather than
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// in their parent blocks. Get the basic block paired with this use
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// of FromReg and check that MI's block dominates it.
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MachineBasicBlock *Pred =
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Where->getOperand(&O - &Where->getOperand(0) + 1).getMBB();
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if (!MDT.dominates(&MBB, Pred))
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continue;
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} else {
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// For a non-PHI, check that MI dominates the instruction in the
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// normal way.
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if (&MI == Where || !MDT.dominates(&MI, Where))
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continue;
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}
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Changed = true;
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DEBUG(dbgs() << "Setting operand " << O << " in " << *Where << " from "
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<< MI << "\n");
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O.setReg(ToReg);
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// If the store's def was previously dead, it is no longer. But the
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// dead flag shouldn't be set yet.
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assert(!MI.getOperand(0).isDead() && "Unexpected dead flag");
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}
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return Changed;
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}
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static bool optimizeStore(MachineBasicBlock &MBB, MachineInstr &MI,
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const MachineRegisterInfo &MRI,
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MachineDominatorTree &MDT) {
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const auto &Stored = MI.getOperand(WebAssembly::StoreValueOperandNo);
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switch (Stored.getType()) {
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case MachineOperand::MO_Register: {
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unsigned ToReg = MI.getOperand(0).getReg();
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unsigned FromReg = Stored.getReg();
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return ReplaceDominatedUses(MBB, MI, FromReg, ToReg, MRI, MDT);
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}
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case MachineOperand::MO_FrameIndex:
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// TODO: optimize.
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return false;
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default:
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report_fatal_error("Store results: store not consuming reg or frame index");
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}
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}
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static bool optimizeCall(MachineBasicBlock &MBB, MachineInstr &MI,
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const MachineRegisterInfo &MRI,
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MachineDominatorTree &MDT,
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const WebAssemblyTargetLowering &TLI,
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const TargetLibraryInfo &LibInfo) {
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MachineOperand &Op1 = MI.getOperand(1);
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if (!Op1.isSymbol())
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return false;
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StringRef Name(Op1.getSymbolName());
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bool callReturnsInput = Name == TLI.getLibcallName(RTLIB::MEMCPY) ||
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Name == TLI.getLibcallName(RTLIB::MEMMOVE) ||
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Name == TLI.getLibcallName(RTLIB::MEMSET);
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if (!callReturnsInput)
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return false;
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LibFunc::Func Func;
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if (!LibInfo.getLibFunc(Name, Func))
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return false;
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const auto &Op2 = MI.getOperand(2);
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switch (Op2.getType()) {
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case MachineOperand::MO_Register: {
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unsigned FromReg = Op2.getReg();
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unsigned ToReg = MI.getOperand(0).getReg();
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if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg))
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report_fatal_error("Store results: call to builtin function with wrong "
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"signature, from/to mismatch");
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return ReplaceDominatedUses(MBB, MI, FromReg, ToReg, MRI, MDT);
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}
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case MachineOperand::MO_FrameIndex:
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// TODO: optimize.
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return false;
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default:
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report_fatal_error("Store results: call to builtin function with wrong "
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"signature, not consuming reg or frame index");
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}
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}
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bool WebAssemblyStoreResults::runOnMachineFunction(MachineFunction &MF) {
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DEBUG({
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dbgs() << "********** Store Results **********\n"
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<< "********** Function: " << MF.getName() << '\n';
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});
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
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const WebAssemblyTargetLowering &TLI =
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*MF.getSubtarget<WebAssemblySubtarget>().getTargetLowering();
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const auto &LibInfo = getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
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bool Changed = false;
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assert(MRI.isSSA() && "StoreResults depends on SSA form");
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for (auto &MBB : MF) {
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DEBUG(dbgs() << "Basic Block: " << MBB.getName() << '\n');
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for (auto &MI : MBB)
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switch (MI.getOpcode()) {
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default:
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break;
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case WebAssembly::STORE8_I32:
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case WebAssembly::STORE16_I32:
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case WebAssembly::STORE8_I64:
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case WebAssembly::STORE16_I64:
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case WebAssembly::STORE32_I64:
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case WebAssembly::STORE_F32:
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case WebAssembly::STORE_F64:
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case WebAssembly::STORE_I32:
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case WebAssembly::STORE_I64:
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Changed |= optimizeStore(MBB, MI, MRI, MDT);
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break;
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case WebAssembly::CALL_I32:
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case WebAssembly::CALL_I64:
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Changed |= optimizeCall(MBB, MI, MRI, MDT, TLI, LibInfo);
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break;
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}
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}
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return Changed;
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}
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