forked from OSchip/llvm-project
135 lines
5.4 KiB
C++
135 lines
5.4 KiB
C++
//===-- WebAssemblyLowerBrUnless.cpp - Lower br_unless --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file lowers br_unless into br_if with an inverted condition.
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///
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/// br_unless is not currently in the spec, but it's very convenient for LLVM
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/// to use. This pass allows LLVM to use it, for now.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssembly.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-lower-br_unless"
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namespace {
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class WebAssemblyLowerBrUnless final : public MachineFunctionPass {
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const char *getPassName() const override {
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return "WebAssembly Lower br_unless";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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public:
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static char ID; // Pass identification, replacement for typeid
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WebAssemblyLowerBrUnless() : MachineFunctionPass(ID) {}
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};
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} // end anonymous namespace
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char WebAssemblyLowerBrUnless::ID = 0;
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FunctionPass *llvm::createWebAssemblyLowerBrUnless() {
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return new WebAssemblyLowerBrUnless();
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}
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bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "********** Lowering br_unless **********\n"
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"********** Function: "
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<< MF.getName() << '\n');
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auto &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
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const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
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auto &MRI = MF.getRegInfo();
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for (auto &MBB : MF) {
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for (auto MII = MBB.begin(); MII != MBB.end();) {
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MachineInstr *MI = &*MII++;
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if (MI->getOpcode() != WebAssembly::BR_UNLESS)
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continue;
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unsigned Cond = MI->getOperand(1).getReg();
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bool Inverted = false;
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// Attempt to invert the condition in place.
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if (MFI.isVRegStackified(Cond)) {
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assert(MRI.hasOneDef(Cond));
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MachineInstr *Def = MRI.getVRegDef(Cond);
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switch (Def->getOpcode()) {
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using namespace WebAssembly;
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case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break;
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case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break;
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case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break;
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case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break;
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case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break;
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case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break;
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case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break;
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case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break;
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case LT_U_I32: Def->setDesc(TII.get(GE_U_I32)); Inverted = true; break;
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case LE_U_I32: Def->setDesc(TII.get(GT_U_I32)); Inverted = true; break;
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case EQ_I64: Def->setDesc(TII.get(NE_I64)); Inverted = true; break;
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case NE_I64: Def->setDesc(TII.get(EQ_I64)); Inverted = true; break;
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case GT_S_I64: Def->setDesc(TII.get(LE_S_I64)); Inverted = true; break;
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case GE_S_I64: Def->setDesc(TII.get(LT_S_I64)); Inverted = true; break;
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case LT_S_I64: Def->setDesc(TII.get(GE_S_I64)); Inverted = true; break;
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case LE_S_I64: Def->setDesc(TII.get(GT_S_I64)); Inverted = true; break;
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case GT_U_I64: Def->setDesc(TII.get(LE_U_I64)); Inverted = true; break;
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case GE_U_I64: Def->setDesc(TII.get(LT_U_I64)); Inverted = true; break;
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case LT_U_I64: Def->setDesc(TII.get(GE_U_I64)); Inverted = true; break;
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case LE_U_I64: Def->setDesc(TII.get(GT_U_I64)); Inverted = true; break;
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case EQ_F32: Def->setDesc(TII.get(NE_F32)); Inverted = true; break;
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case NE_F32: Def->setDesc(TII.get(EQ_F32)); Inverted = true; break;
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case EQ_F64: Def->setDesc(TII.get(NE_F64)); Inverted = true; break;
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case NE_F64: Def->setDesc(TII.get(EQ_F64)); Inverted = true; break;
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default: break;
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}
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}
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// If we weren't able to invert the condition in place. Insert an
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// expression to invert it.
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if (!Inverted) {
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unsigned ZeroReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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MFI.stackifyVReg(ZeroReg);
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BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::CONST_I32),
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ZeroReg)
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.addImm(0);
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unsigned Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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MFI.stackifyVReg(Tmp);
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BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQ_I32), Tmp)
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.addReg(Cond)
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.addReg(ZeroReg);
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Cond = Tmp;
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Inverted = true;
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}
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// The br_unless condition has now been inverted. Insert a br_if and
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// delete the br_unless.
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assert(Inverted);
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BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::BR_IF))
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.addOperand(MI->getOperand(0))
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.addReg(Cond);
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MBB.erase(MI);
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}
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}
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return true;
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}
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