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llvm-project/llvm/test/CodeGen/Thumb2
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Hendrik Greving a92ed167f2 [ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4. 
Adds MVT::v128i2, MVT::v64i4, and implied MVT::i2, MVT::i4.

Keeps MVT::i2, MVT::i4 lowering actions as expand, which should be
removed once targets set this explicitly.

Adjusts 11 lit tests to reflect slightly different behavior during
DAG combine.

Differential Revision: https://reviews.llvm.org/D125247
 		2022-06-02 00:49:11 +00:00
..
LowOverheadLoops Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
mve-intrinsics [ARM] Use v2i1 for MVE and CDE intrinsics 2021-12-03 15:27:58 +00:00
2009-07-17-CrossRegClassCopy.ll
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2009-07-21-ISelBug.ll
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2009-07-23-CPIslandBug.ll
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2009-07-30-PEICrash.ll
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2009-08-01-WrongLDRBOpc.ll
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2009-08-02-CoalescerBug.ll
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2009-08-04-CoalescerAssert.ll
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2009-08-04-CoalescerBug.ll [SimplifyCFG] Teach removeUndefIntroducingPredecessor to preserve DomTree 2021-01-02 01:01:20 +03:00
2009-08-04-ScavengerAssert.ll
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2009-08-04-SubregLoweringBug.ll OpaquePtr: Bulk update tests to use typed sret 2020-11-20 17:58:26 -05:00
2009-08-04-SubregLoweringBug2.ll
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2009-08-04-SubregLoweringBug3.ll
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2009-08-06-SpDecBug.ll
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2009-08-07-CoalescerBug.ll
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2009-08-07-NeonFPBug.ll
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2009-08-08-ScavengerAssert.ll
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2009-08-10-ISelBug.ll
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2009-08-21-PostRAKill4.ll
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2009-09-01-PostRAProlog.ll
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2009-10-15-ITBlockBranch.ll
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2009-11-01-CopyReg2RegBug.ll
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2009-11-11-ScavengerAssert.ll
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2009-11-13-STRDBug.ll
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2009-12-01-LoopIVUsers.ll
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2010-01-06-TailDuplicateLabels.ll
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2010-01-19-RemovePredicates.ll
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2010-02-11-phi-cycle.ll [CPG][ARM] Optimize towards branch on zero in codegenprepare 2021-05-16 17:54:06 +01:00
2010-02-24-BigStack.ll
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2010-03-08-addi12-ccout.ll
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2010-03-15-AsmCCClobber.ll
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2010-04-15-DynAllocBug.ll
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2010-04-26-CopyRegCrash.ll
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2010-05-24-rsbs.ll
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2010-06-14-NEONCoalescer.ll
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2010-06-19-ITBlockCrash.ll
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2010-06-21-TailMergeBug.ll
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2010-08-10-VarSizedAllocaBug.ll
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2010-11-22-EpilogueBug.ll
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2010-12-03-AddSPNarrowing.ll
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2011-04-21-FILoweringBug.ll
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2011-06-07-TwoAddrEarlyClobber.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
2011-12-16-T2SizeReduceAssert.ll
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2012-01-13-CBNZBug.ll
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2013-02-19-tail-call-register-hint.ll
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2013-03-02-vduplane-nonconstant-source-index.ll
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2013-03-06-vector-sext-operand-scalarize.ll
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aapcs.ll
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abs.ll [SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y). 2022-02-20 21:11:23 -08:00
active_lane_mask.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
aligned-constants.ll
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aligned-nonfallthrough.ll [ARM] Improve detection of fallthough when aligning blocks 2021-09-27 11:21:21 +01:00
aligned-spill.ll
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bfi.ll
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bfx.ll
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bicbfi.ll
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bti-const-island-multiple-jump-tables.mir Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
bti-const-island.mir Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
bti-entry-blocks.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
bti-indirect-branches.ll Update test for changes in f0ea9c9cec / D124552 2022-05-10 13:25:38 -07:00
bti-jump-table.mir Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
bti-outliner-1.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
bti-outliner-2.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
bti-outliner-cost-1.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
bti-outliner-cost-2.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
bti-pac-replace-1.mir Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
bti-pac-replace-2.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
bug-subw.ll
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buildvector-crash.ll
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call-site-info-update.ll
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carry.ll
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cbnz.ll
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cde-gpr.ll
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cde-vec.ll [ARM] Use v2i1 for MVE and CDE intrinsics 2021-12-03 15:27:58 +00:00
cde-vfp.ll
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cmp-frame.ll
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constant-hoisting.ll [ARM] Fix IT block generation after Thumb2SizeReduce with -Oz 2020-10-29 15:17:31 +00:00
constant-islands-cbz.ll
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constant-islands-cbz.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
constant-islands-cbzundef.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
constant-islands-jump-table.ll
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constant-islands-ldrsb.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
constant-islands-new-island-padding.ll
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constant-islands-new-island.ll
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constant-islands.ll OpaquePtr: Update more tests to use typed sret 2020-11-20 20:08:43 -05:00
cortex-fp.ll
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crash.ll
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cross-rc-coalescing-1.ll
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cross-rc-coalescing-2.ll
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csel.ll [ARM] Ensure CSINC has one use in CSINV combine 2021-04-29 10:59:14 +01:00
div.ll
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emit-unwinding.ll
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fir.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
float-cmp.ll
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float-intrinsics-double.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
float-intrinsics-float.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
float-ops.ll [ARM] CSEL generation 2020-07-16 11:10:53 +01:00
fp16-stacksplot.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
frame-index-addrmode-t2i8s4.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
frame-pointer.ll
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frameless.ll
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frameless2.ll
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high-reg-spill.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ifcvt-cbz.mir
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ifcvt-compare.ll
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ifcvt-dead-predicate.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
ifcvt-minsize.ll
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ifcvt-neon-deprecated.mir
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ifcvt-no-branch-predictor.ll [ARM] Make tests less dependent on scheduling. NFC 2020-11-05 08:26:55 +00:00
ifcvt-rescan-bug-2016-08-22.ll
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ifcvt-rescan-diamonds.ll [ARM] Undeprecate complex IT blocks 2022-02-07 15:47:53 +00:00
inflate-regs.ll
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inline-asm-i-constraint-i1.ll
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inlineasm-error-t-toofewregs-mve.ll
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inlineasm-mve.ll
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inlineasm.ll
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intrinsics-cc.ll Update @llvm.powi to handle different int sizes for the exponent 2021-06-17 09:38:28 +02:00
intrinsics-coprocessor.ll
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large-call.ll
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large-stack.ll
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ldr-str-imm12.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
lit.local.cfg
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longMACt.ll
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lsll0.ll [ARM] Ensure instructions are simplified prior to GatherScatter lowering. 2021-06-10 20:18:12 +01:00
lsr-deficiency.ll
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m4-sched-ldr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
m4-sched-regs.ll
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machine-licm.ll
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mul_const.ll
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mve-abs.ll [LegalizeTypes][ARM][X86] Change ExpandIntRes_ABS to use sra+xor+sub. 2022-03-07 11:28:32 -08:00
mve-basic.ll
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mve-be.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-bitarith.ll
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mve-bitcasts.ll
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mve-bitreverse.ll
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mve-blockplacement.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-bswap.ll
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mve-ctlz.ll [ARM] Fold away unnecessary CSET/CMPZ 2021-11-27 19:07:16 +00:00
mve-ctpop.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-cttz.ll [ARM] Fold away unnecessary CSET/CMPZ 2021-11-27 19:07:16 +00:00
mve-div-expand.ll [ARM] Fix vcvtb/t.f16 input liveness 2022-05-25 12:16:26 +01:00
mve-extractelt.ll
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mve-extractstore.ll [ARM] Optimize fp store of extract to integer store if already available. 2021-02-12 18:34:58 +00:00
mve-float16regloops.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
mve-float32regloops.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
mve-fma-loops.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
mve-fmas.ll [ARM] CSINC/CSINV patterns from CMOV 2021-11-27 20:21:41 +00:00
mve-fmath.ll [ARM] Fix vcvtb/t.f16 input liveness 2022-05-25 12:16:26 +01:00
mve-fp-negabs.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-fp16convertloops.ll [ARM] Generate VDUP(Const) from constant buildvectors 2021-06-08 20:51:33 +01:00
mve-fpclamptosat_vec.ll [DAG] Create fptoui.sat from clamped fptoui 2022-01-26 08:37:44 +00:00
mve-fptosi-sat-vector.ll [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits 2022-05-14 09:50:01 +01:00
mve-fptoui-sat-vector.ll [DAG] Enable ISD::SHL SimplifyMultipleUseDemandedBits handling inside SimplifyDemandedBits 2022-05-14 09:50:01 +01:00
mve-frint.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-gather-increment.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-gather-ind8-unscaled.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-gather-ind16-scaled.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-gather-ind16-unscaled.ll [ARM] Create VMOVRRD from adjacent vector extracts 2021-04-20 15:15:43 +01:00
mve-gather-ind32-scaled.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-gather-ind32-unscaled.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-gather-optimisation-deep.ll [ARM] Fix GatherScatter AddLikeOr condition 2021-11-15 09:44:41 +00:00
mve-gather-ptrs.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-gather-scatter-opt.ll [ARM] Add some opaque pointer gather/scatter tests. NFC 2021-07-07 22:03:53 +01:00
mve-gather-scatter-optimisation.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-gather-scatter-ptr-address.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-gather-scatter-tailpred.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-gather-tailpred.ll [ARM] Don't handle low overhead branches in AnalyzeBranch 2021-01-18 17:16:07 +00:00
mve-gather-unused.ll [ARM] Ensure instructions are simplified prior to GatherScatter lowering. 2021-06-10 20:18:12 +01:00
mve-gatherscatter-mmo.ll [ARM] Use v2i1 for MVE and CDE intrinsics 2021-12-03 15:27:58 +00:00
mve-halving.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-laneinterleaving-cost.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-laneinterleaving.ll [ARM] Delay creation of MVE Imm shifts to legalization 2022-05-04 22:12:09 +01:00
mve-ldst-offset.ll
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mve-ldst-postinc.ll
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mve-ldst-preinc.ll
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mve-ldst-regimm.ll
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mve-loadstore.ll [ARM] Remove unused check labels. NFC 2020-11-12 08:37:46 +00:00
mve-masked-ldst-offset.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
mve-masked-ldst-postinc.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
mve-masked-ldst-preinc.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
mve-masked-ldst.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-masked-load.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-masked-store-mmo.ll [SDAG] Use UnknownSize for masked load/store MMO size 2021-11-23 09:47:56 +00:00
mve-masked-store.ll [ARM] Fix vcvtb/t.f16 input liveness 2022-05-25 12:16:26 +01:00
mve-memtp-branch.ll [ARM] Revert WLSTP to DLSTP if the target block is out of range 2021-08-02 10:59:52 +01:00
mve-memtp-loop.ll [ARM] Revert WLSTP to DLSTP if the target block is out of range 2021-08-02 10:59:52 +01:00
mve-minmax.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-minmaxi.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-multivec-spill.ll [LiveIntervals] Repair subreg ranges in processTiedPairs 2021-09-28 08:10:16 +01:00
mve-neg.ll [ARM] Create VMOVRRD from adjacent vector extracts 2021-04-20 15:15:43 +01:00
mve-nofloat.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-nounrolledremainder.ll [ARM] KnownBits for CSINC/CSNEG/CSINV 2021-03-04 08:40:20 +00:00
mve-phireg.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-postinc-dct.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
mve-postinc-distribute.ll [ARM] Improve WLS lowering 2021-03-11 17:56:19 +00:00
mve-postinc-distribute.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-postinc-lsr.ll [SimplifyCFG] performBranchToCommonDestFolding(): require block-closed SSA form for bonus instructions (PR51125) 2021-09-09 12:28:09 +03:00
mve-pred-and.ll [ARM] Peek through And 1 in IsCMPZCSINC 2021-12-08 15:40:23 +00:00
mve-pred-bitcast.ll [ARM] Peek through And 1 in IsCMPZCSINC 2021-12-08 15:40:23 +00:00
mve-pred-build-const.ll [ARM] Make MVE v2i1 predicates legal 2021-12-03 14:05:41 +00:00
mve-pred-build-var.ll [ARM] Make MVE v2i1 predicates legal 2021-12-03 14:05:41 +00:00
mve-pred-const.ll [ARM] Make MVE v2i1 predicates legal 2021-12-03 14:05:41 +00:00
mve-pred-constfold.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
mve-pred-convert.ll
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mve-pred-ext.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-pred-loadstore.ll [ARM] Peek through And 1 in IsCMPZCSINC 2021-12-08 15:40:23 +00:00
mve-pred-not.ll [ARM] Peek through And 1 in IsCMPZCSINC 2021-12-08 15:40:23 +00:00
mve-pred-or.ll [ARM] Fold away CMP/CSINC from CMOV 2021-12-19 21:53:50 +00:00
mve-pred-selectop.ll [ARM] Update target triple in tests. NFC 2020-10-30 15:06:49 +00:00
mve-pred-selectop2.ll [ARM] Add fma and update fadd/fmul predicated select tests. NFC 2021-11-24 09:51:33 +00:00
mve-pred-selectop3.ll [ARM] Fold (fadd x, (vselect c, y, -1.0)) into (vselect c, (fadd x, y), x) 2021-11-24 10:41:00 +00:00
mve-pred-shuffle.ll [ARM] Peek through And 1 in IsCMPZCSINC 2021-12-08 15:40:23 +00:00
mve-pred-spill.ll [ARM] Peek through And 1 in IsCMPZCSINC 2021-12-08 15:40:23 +00:00
mve-pred-threshold.ll [ARM] Remove DLS lr, lr 2021-02-02 11:09:31 +00:00
mve-pred-vctpvpsel.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-pred-vselect.ll [ARM] Fold away CMP/CSINC from CMOV 2021-12-19 21:53:50 +00:00
mve-pred-xor.ll [ARM] Fold away CMP/CSINC from CMOV 2021-12-19 21:53:50 +00:00
mve-qrintr.ll [ARM] Add more MVE intrinsics to sink splats to 2021-09-30 14:41:23 +01:00
mve-qrintrsplat.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-satmul-loops.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-saturating-arith.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-scatter-increment.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-scatter-ind8-unscaled.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-scatter-ind16-scaled.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-scatter-ind16-unscaled.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-scatter-ind32-scaled.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-scatter-ind32-unscaled.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-scatter-ptrs.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-selectcc.ll [ARM] Handle splats of constants for MVE qr instruction 2021-12-17 09:16:28 +00:00
mve-sext-masked-load.ll [LiveIntervals] Remove unused subreg ranges in repairIntervalsInRange 2021-09-30 09:15:10 +01:00
mve-sext.ll [ARM] Introduce MVEEXT ISel lowering 2021-07-13 07:21:20 +01:00
mve-shifts-scalar.ll [ARM] Remove DLS lr, lr 2021-02-02 11:09:31 +00:00
mve-shifts.ll [ARM] Generate VDUP(Const) from constant buildvectors 2021-06-08 20:51:33 +01:00
mve-shuffle.ll [DAG]Introduce llvm::processShuffleMasks and use it for shuffles in DAG Type Legalizer. 2022-04-20 09:37:16 -07:00
mve-shuffleext.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-shufflemov.ll [DAG][PowerPC] Combine shuffle(bitcast(X), Mask) to bitcast(shuffle(X, Mask')) 2022-05-06 10:50:31 +01:00
mve-simple-arith.ll RegAllocGreedy: Account for reserved registers in num regs heuristic 2021-09-14 21:00:29 -04:00
mve-soft-float-abi.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-stack.ll
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mve-stacksplot.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-tailpred-loopinvariant.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
mve-tp-loop.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vabd.ll [ARM] Create VMOVRRD from adjacent vector extracts 2021-04-20 15:15:43 +01:00
mve-vabdus.ll [LegalizeTypes][ARM][X86] Change ExpandIntRes_ABS to use sra+xor+sub. 2022-03-07 11:28:32 -08:00
mve-vaddqr.ll [ARM] Use half directly for args/return types in test. NFC 2021-01-25 17:50:19 +00:00
mve-vaddv.ll [ARM] Attempt to distribute reductions 2021-07-30 14:48:31 +01:00
mve-vcmp.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-vcmpf.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-vcmpfr.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-vcmpfz.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-vcmpr.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-vcmpz.ll [ARM] Peek through And 1 in IsCMPZCSINC 2021-12-08 15:40:23 +00:00
mve-vcreate.ll [ARM] Simplify VMOVRRD from extracts of buildvectors 2021-02-01 16:09:25 +00:00
mve-vctp.ll [ARM] Use v2i1 for MVE and CDE intrinsics 2021-12-03 15:27:58 +00:00
mve-vcvt-fixed-to-float.ll [ARM] Transform a floating-point to fixed-point conversion to a VCVT_fix 2021-07-01 15:10:40 +01:00
mve-vcvt-float-to-fixed.ll [SelectionDAG] Add FP_TO_UINT_SAT/FP_TO_SINT_SAT to computeKnownBits/computeNumSignBits. 2022-01-09 17:48:05 -08:00
mve-vcvt.ll [ARM] Fix vcvtb/t.f16 input liveness 2022-05-25 12:16:26 +01:00
mve-vcvt16.ll [ARM] Fix vcvtb/t.f16 input liveness 2022-05-25 12:16:26 +01:00
mve-vdup.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-vecreduce-add.ll [ARM] Extend more reductions during lowering 2021-07-19 08:58:03 +01:00
mve-vecreduce-addpred.ll [ARM] Peek through And 1 in IsCMPZCSINC 2021-12-08 15:40:23 +00:00
mve-vecreduce-bit.ll [ARM] Create VMOVRRD from adjacent vector extracts 2021-04-20 15:15:43 +01:00
mve-vecreduce-fadd.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-vecreduce-fminmax.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-vecreduce-fmul.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-vecreduce-loops.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-vecreduce-mla.ll [ARM] Switch order of creating VADDV and VMLAV. 2021-07-31 16:28:52 +01:00
mve-vecreduce-mlapred.ll [ARM] Peek through And 1 in IsCMPZCSINC 2021-12-08 15:40:23 +00:00
mve-vecreduce-mul.ll [ARM] Create VMOVRRD from adjacent vector extracts 2021-04-20 15:15:43 +01:00
mve-vecreduce-slp.ll [ARM] Fix DAG combine loop in reduction distribution 2021-08-12 16:37:39 +01:00
mve-vector-spill.ll Reapply "RegAllocFast: Rewrite and improve" 2020-09-30 10:35:25 -04:00
mve-vfma.ll
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mve-vhadd.ll [ARM] MVE hadd and rhadd 2022-02-14 11:55:40 +00:00
mve-vhaddsub.ll
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mve-vidup.ll [ARM] Recognize VIDUP from BUILDVECTORs of additions 2021-04-27 19:33:24 +01:00
mve-vld2-post.ll [DAG][PowerPC] Combine shuffle(bitcast(X), Mask) to bitcast(shuffle(X, Mask')) 2022-05-06 10:50:31 +01:00
mve-vld2.ll [DAG][PowerPC] Combine shuffle(bitcast(X), Mask) to bitcast(shuffle(X, Mask')) 2022-05-06 10:50:31 +01:00
mve-vld3.ll [DAG]Introduce llvm::processShuffleMasks and use it for shuffles in DAG Type Legalizer. 2022-04-20 09:37:16 -07:00
mve-vld4-post.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-vld4.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-vldshuffle.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-vldst4.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-vmaxnma-commute.ll [ARM] Improve WLS lowering 2021-03-11 17:56:19 +00:00
mve-vmaxnma-tailpred.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
mve-vmaxv-vminv-scalar.ll [ARM] CSINC/CSINV patterns from CMOV 2021-11-27 20:21:41 +00:00
mve-vmaxv.ll [llvm][mlir] Promote the experimental reduction intrinsics to be first class intrinsics. 2020-10-07 10:36:44 -07:00
mve-vmla.ll
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mve-vmovimm.ll [ARM] Make MVE v2i1 predicates legal 2021-12-03 14:05:41 +00:00
mve-vmovlloop.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
mve-vmovn.ll [ARM][AArch64] Add some extra shuffle conversion test coverage. NFC 2022-05-05 15:27:44 +01:00
mve-vmovnstore.ll [ARM] Mark i64 and f64 shuffles as Custom for MVE 2022-02-06 16:17:06 +00:00
mve-vmulh.ll [ARM] Add extra vabd, vhadd and vmulh tests. NFC 2022-02-06 14:12:28 +00:00
mve-vmull-loop.ll [ARM] Create VMOVRRD from adjacent vector extracts 2021-04-20 15:15:43 +01:00
mve-vmull-splat.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-vmull.ll
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mve-vmulqr.ll
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mve-vmvnimm.ll [ARM] Generate VDUP(Const) from constant buildvectors 2021-06-08 20:51:33 +01:00
mve-vpsel.ll [ARM] Make MVE v2i1 predicates legal 2021-12-03 14:05:41 +00:00
mve-vpt-2-blocks-1-pred.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-2-blocks-2-preds.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-2-blocks-ctrl-flow.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-2-blocks-non-consecutive-ins.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-2-blocks.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-3-blocks-kill-vpr.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-block-1-ins.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-block-2-ins.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-block-4-ins.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-block-debug.mir [MachineInstr] Don't include debug uses in bundle header (PR52817) 2022-01-17 10:43:21 +01:00
mve-vpt-block-elses.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-block-fold-vcmp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-block-kill.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-block-optnone.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-blocks.ll
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mve-vpt-from-intrinsics.ll [InstCombine] Move target-specific inst combining 2020-07-22 15:59:49 +02:00
mve-vpt-nots.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vpt-optimisations.mir ARM: Fix using undefined virtual registers in test 2022-05-04 00:05:49 +01:00
mve-vpt-preuse.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-vqdmulh-minmax.ll [ARM] Fix VQDMULH fold for scalar smin 2021-08-21 16:33:18 +01:00
mve-vqdmulh.ll [ARM] CSINC/CSINV patterns from CMOV 2021-11-27 20:21:41 +00:00
mve-vqmovn-combine.ll [ARM] Update target triple in tests. NFC 2020-10-30 15:06:49 +00:00
mve-vqmovn.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-vqshrn.ll [ARM] Extend IsCMPZCSINC to handle CMOV 2021-12-27 14:15:03 +00:00
mve-vselect-constants.ll [ARM] Peek through And 1 in IsCMPZCSINC 2021-12-08 15:40:23 +00:00
mve-vst2-post.ll [ARM] Mark i64 and f64 shuffles as Custom for MVE 2022-02-06 16:17:06 +00:00
mve-vst2.ll [ARM] Mark i64 and f64 shuffles as Custom for MVE 2022-02-06 16:17:06 +00:00
mve-vst3.ll [DAG][PowerPC] Combine shuffle(bitcast(X), Mask) to bitcast(shuffle(X, Mask')) 2022-05-06 10:50:31 +01:00
mve-vst4-post.ll [ARM] Mark i64 and f64 shuffles as Custom for MVE 2022-02-06 16:17:06 +00:00
mve-vst4.ll [DAG][PowerPC] Combine shuffle(bitcast(X), Mask) to bitcast(shuffle(X, Mask')) 2022-05-06 10:50:31 +01:00
mve-vsubqr.ll
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mve-widen-narrow.ll [ARM] Introduce MVEEXT ISel lowering 2021-07-13 07:21:20 +01:00
mve-wls-block-placement.mir [ARM] Fix Arm block placement creating branches after jump tables. 2021-09-25 11:32:25 +01:00
mve-zext-masked-load.ll [ARM] Move VPTBlock pass after post-ra scheduling 2021-11-04 18:42:12 +00:00
pacbti-m-basic.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
pacbti-m-indirect-tail-call.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
pacbti-m-outliner-1.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
pacbti-m-outliner-2.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
pacbti-m-outliner-3.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
pacbti-m-outliner-4.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
pacbti-m-outliner-5.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
pacbti-m-overalign.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
pacbti-m-unsupported-arch.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
pacbti-m-varargs-1.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
pacbti-m-varargs-2.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
pacbti-m-vla.ll Support the min of module flags when linking, use for AArch64 BTI/PAC-RET 2022-04-13 09:31:51 +02:00
peephole-addsub.mir
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peephole-cmp.mir
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phi_prevent_copy.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
pic-load.ll [ARM] Remove more unused check prefixes, NFC 2020-11-14 15:37:53 +00:00
postinc-distribute.mir [ARM] Introduce i8neg and i8pos addressing modes 2021-12-02 17:10:26 +00:00
pr52817.ll [MachineInstr] Don't include debug uses in bundle header (PR52817) 2022-01-17 10:43:21 +01:00
scavenge-lr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
schedm7-hazard.ll [ARM] Add bank conflict hazarding 2020-12-23 14:00:59 +00:00
segmented-stacks.ll [ARM] Only update the successor edges for immediate predecessors of PrologueMBB 2022-05-03 12:36:35 +01:00
setjmp_longjmp.ll [NFC][Codegen] Autogenerate Thumb2/setjmp_longjmp.ll test 2021-06-24 21:35:05 +03:00
shift_parts.ll
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srem-seteq-illegal-types.ll [ValueTypes] Define MVTs for v128i2/v64i4 as well as i2 and i4. 2022-06-02 00:49:11 +00:00
stack_guard_remat.ll [CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC. 2022-02-18 16:10:56 +00:00
store-prepostinc.mir [ARM] Correct range in isLegalAddressImm 2021-12-02 11:33:40 +00:00
swp-exitbranchdir.mir Reapply [CodeGen][ARM] Enable Swing Module Scheduling for ARM 2022-04-29 10:54:39 -07:00
swp-fixedii-le.mir [ARM] Recognize t2LoopEnd for software pipelining 2022-05-26 09:55:42 -07:00
swp-fixedii.mir Reapply [CodeGen][ARM] Enable Swing Module Scheduling for ARM 2022-04-29 10:54:39 -07:00
t2-teq-reduce.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
t2peephole-t2ADDrr-to-t2ADDri.ll
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t2sizereduction.mir Revert "[NFC] remove explicit default value for strboolattr attribute in tests" 2021-05-24 19:43:40 +02:00
tail-call-r9.ll
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tbb-removeadd.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
thumb2-adc.ll
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thumb2-add.ll
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thumb2-add2.ll
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thumb2-add3.ll
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thumb2-add4.ll
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thumb2-add5.ll
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thumb2-add6.ll
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thumb2-and.ll
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thumb2-and2.ll
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thumb2-asr.ll
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thumb2-asr2.ll
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thumb2-bcc.ll
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thumb2-bfc.ll
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thumb2-bic.ll
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thumb2-branch.ll Revert "[BPI] Improve static heuristics for integer comparisons" 2020-08-17 20:44:33 +02:00
thumb2-call-tc.ll
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thumb2-call.ll
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thumb2-cbnz.ll
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thumb2-clz.ll
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thumb2-cmn.ll
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thumb2-cmn2.ll
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thumb2-cmp.ll
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thumb2-cpsr-liveness.ll
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thumb2-eor.ll
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thumb2-eor2.ll
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thumb2-execute-only-prologue.ll [ARM] Clean up a test check from D125604. NFC 2022-05-18 16:12:08 +01:00
thumb2-ifcvt1-tc.ll
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thumb2-ifcvt1.ll [ARM] Undeprecate complex IT blocks 2022-02-07 15:47:53 +00:00
thumb2-ifcvt2.ll [ARM] Undeprecate complex IT blocks 2022-02-07 15:47:53 +00:00
thumb2-ifcvt3.ll [ARM] Undeprecate complex IT blocks 2022-02-07 15:47:53 +00:00
thumb2-jtb.ll
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thumb2-ldm.ll
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thumb2-ldr.ll
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thumb2-ldr_ext.ll
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thumb2-ldr_post.ll
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thumb2-ldr_pre.ll
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thumb2-ldrb.ll
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thumb2-ldrd.ll
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thumb2-ldrh.ll
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thumb2-lsl.ll
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thumb2-lsl2.ll
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thumb2-lsr.ll
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thumb2-lsr2.ll
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thumb2-lsr3.ll
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thumb2-mla.ll
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thumb2-mls.ll
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thumb2-mov.ll
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thumb2-mul.ll
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thumb2-mulhi.ll
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thumb2-mvn.ll
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thumb2-mvn2.ll
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thumb2-neg.ll
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thumb2-orn.ll
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thumb2-orn2.ll
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thumb2-orr.ll
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thumb2-orr2.ll
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thumb2-pack.ll
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thumb2-rev.ll
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thumb2-rev16.ll
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thumb2-ror.ll
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thumb2-rsb.ll
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thumb2-rsb2.ll
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thumb2-sbc.ll
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thumb2-select.ll
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thumb2-select_xform.ll
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thumb2-shifter.ll
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thumb2-smla.ll
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thumb2-smul.ll
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thumb2-spill-q.ll
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thumb2-str.ll
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thumb2-str_post.ll
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thumb2-str_pre.ll
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thumb2-strb.ll
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thumb2-strh.ll
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thumb2-sub.ll
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thumb2-sub2.ll
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thumb2-sub3.ll
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thumb2-sub4.ll
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thumb2-sub5.ll
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thumb2-sxt-uxt.ll
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thumb2-sxt_rot.ll [Thumb2] Regenerate ext + rot tests 2021-11-21 18:33:28 +00:00
thumb2-tbb.ll
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thumb2-tbh.ll
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thumb2-teq.ll [DAG] SimplifySetCC - relax fold (X^C1) == C2 --> X == C1^C2 2022-04-06 09:18:08 +01:00
thumb2-teq2.ll [Thumb2] Regenerate thumb2-teq2 tests 2022-04-04 12:48:20 +01:00
thumb2-tst.ll
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thumb2-tst2.ll
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thumb2-uxt_rot.ll [Thumb2] Regenerate ext + rot tests 2021-11-21 18:33:28 +00:00
thumb2-uxtb.ll [ARM][Thumb2] Refresh UXTB16 tests to match optimized IR from instcombine 2022-06-01 15:28:19 +01:00
tls1.ll [test] Add explicit dso_local to definitions in ELF static relocation model tests 2020-12-30 15:47:16 -08:00
tls2.ll
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tpsoft.ll [SimplifyCFG] Tail-merging all blocks with `ret` terminator 2021-06-24 13:15:39 +03:00
umulo-64-legalisation-lowering.ll
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umulo-128-legalisation-lowering.ll Do not generate calls to the 128-bit function __multi3() on 32-bit ARM 2021-06-11 11:45:21 +01:00
unreachable-large-offset-gep.ll
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urem-seteq-illegal-types.ll Support {S,U}REMEqFold before legalization 2021-04-01 01:35:41 +03:00
v8_IT_1.ll
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v8_IT_2.ll
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v8_IT_3.ll [ARM] Undeprecate complex IT blocks 2022-02-07 15:47:53 +00:00
v8_IT_4.ll [ARM] Undeprecate complex IT blocks 2022-02-07 15:47:53 +00:00
v8_IT_5.ll [ARM] Undeprecate complex IT blocks 2022-02-07 15:47:53 +00:00
v8_IT_6.ll
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vmovdrroffset.ll [ARM] Fix pointer offset when splitting stores from VMOVDRR 2020-10-03 16:47:50 +01:00
vqabs.ll
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vqneg.ll
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