Artem Tamazov e2762423c2 [AMDGPU][llvm-mc] s_setreg* - Fix order of operands ... Order should match the sp3 syntax, where destination (simm16 denoting the hwreg) is coming first. Differential Revision: http://reviews.llvm.org/D19161 llvm-svn: 266617		2016-04-18 14:54:26 +00:00
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AArch64	[AArch64] Add ARMv8.2-A FP16 vector instructions	2015-12-08 12:16:10 +00:00
AMDGPU	[AMDGPU][llvm-mc] s_setreg* - Fix order of operands	2016-04-18 14:54:26 +00:00
ARM	[ARM] Add new system registers to ARMv8-M Baseline/Mainline	2016-01-25 11:25:36 +00:00
Hexagon	[Hexagon] Fixing store instructions and reenabling a few more tests.	2015-11-10 00:22:00 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	Summary:	2016-04-14 13:43:17 +00:00
PowerPC	[PowerPC] Basic support for P9 byte comparison and count trailing zero insns	2016-04-13 18:51:18 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Add SVC instruction	2016-04-11 14:35:39 +00:00
X86	AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . Change memory operand parser handling.	2016-02-25 13:30:17 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00