forked from OSchip/llvm-project
42 lines
1.2 KiB
LLVM
42 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-zfh \
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; RUN: -verify-machineinstrs -target-abi lp64f | \
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; RUN: FileCheck -check-prefix=RV64IZFH %s
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; RUN: llc < %s -mtriple=riscv64 -mattr=+d \
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; RUN: -mattr=+experimental-zfh -verify-machineinstrs -target-abi lp64d | \
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; RUN: FileCheck -check-prefix=RV64IDZFH %s
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; These intrinsics require half and i64 to be legal types.
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declare i64 @llvm.llrint.i64.f16(half)
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define i64 @llrint_f16(half %a) nounwind {
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; RV64IZFH-LABEL: llrint_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.l.h a0, fa0
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: llrint_f16:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: fcvt.l.h a0, fa0
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; RV64IDZFH-NEXT: ret
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%1 = call i64 @llvm.llrint.i64.f16(half %a)
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ret i64 %1
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}
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declare i64 @llvm.llround.i64.f16(half)
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define i64 @llround_f16(half %a) nounwind {
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; RV64IZFH-LABEL: llround_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: llround_f16:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rmm
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; RV64IDZFH-NEXT: ret
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%1 = call i64 @llvm.llround.i64.f16(half %a)
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ret i64 %1
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}
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