forked from OSchip/llvm-project
223 lines
8.1 KiB
LLVM
223 lines
8.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -disable-strictnode-mutation -target-abi ilp32f < %s \
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; RUN: | FileCheck -check-prefix=RV32IZFH %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -disable-strictnode-mutation -target-abi lp64f < %s \
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; RUN: | FileCheck -check-prefix=RV64IZFH %s
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; FIXME: We can't test without Zfh because soft promote legalization isn't
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; implemented in SelectionDAG for STRICT nodes.
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define half @fadd_h(half %a, half %b) nounwind strictfp {
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; RV32IZFH-LABEL: fadd_h:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fadd_h:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.fadd.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.fadd.f16(half, half, metadata, metadata)
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define half @fsub_h(half %a, half %b) nounwind strictfp {
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; RV32IZFH-LABEL: fsub_h:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fsub.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fsub_h:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fsub.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.fsub.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.fsub.f16(half, half, metadata, metadata)
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define half @fmul_h(half %a, half %b) nounwind strictfp {
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; RV32IZFH-LABEL: fmul_h:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmul.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fmul_h:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmul.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.fmul.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.fmul.f16(half, half, metadata, metadata)
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define half @fdiv_h(half %a, half %b) nounwind strictfp {
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; RV32IZFH-LABEL: fdiv_h:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fdiv.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fdiv_h:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fdiv.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.fdiv.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.fdiv.f16(half, half, metadata, metadata)
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define half @fsqrt_h(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: fsqrt_h:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fsqrt.h fa0, fa0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fsqrt_h:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fsqrt.h fa0, fa0
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
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; FIXME: fminnum/fmaxnum need libcalls to handle SNaN, but we don't have f16
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; libcalls and don't support promotion yet.
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;define half @fmin_h(half %a, half %b) nounwind strictfp {
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; %1 = call half @llvm.experimental.constrained.minnum.f16(half %a, half %b, metadata !"fpexcept.strict") strictfp
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; ret half %1
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;}
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;declare half @llvm.experimental.constrained.minnum.f16(half, half, metadata) strictfp
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;
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;define half @fmax_h(half %a, half %b) nounwind strictfp {
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; %1 = call half @llvm.experimental.constrained.maxnum.f16(half %a, half %b, metadata !"fpexcept.strict") strictfp
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; ret half %1
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;}
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;declare half @llvm.experimental.constrained.maxnum.f16(half, half, metadata) strictfp
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define half @fmadd_h(half %a, half %b, half %c) nounwind strictfp {
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; RV32IZFH-LABEL: fmadd_h:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fmadd_h:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) strictfp
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define half @fmsub_h(half %a, half %b, half %c) nounwind strictfp {
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; RV32IZFH-LABEL: fmsub_h:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fmsub_h:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
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; RV64IZFH-NEXT: ret
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%c_ = fadd half 0.0, %c ; avoid negation using xor
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%negc = fneg half %c_
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%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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define half @fnmadd_h(half %a, half %b, half %c) nounwind strictfp {
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; RV32IZFH-LABEL: fnmadd_h:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
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; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fnmadd_h:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
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; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
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; RV64IZFH-NEXT: ret
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%a_ = fadd half 0.0, %a
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%c_ = fadd half 0.0, %c
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%nega = fneg half %a_
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%negc = fneg half %c_
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%1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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define half @fnmadd_h_2(half %a, half %b, half %c) nounwind strictfp {
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; RV32IZFH-LABEL: fnmadd_h_2:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft1, fa1, ft0
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; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fnmadd_h_2:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft1, fa1, ft0
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; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
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; RV64IZFH-NEXT: ret
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%b_ = fadd half 0.0, %b
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%c_ = fadd half 0.0, %c
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%negb = fneg half %b_
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%negc = fneg half %c_
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%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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define half @fnmsub_h(half %a, half %b, half %c) nounwind strictfp {
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; RV32IZFH-LABEL: fnmsub_h:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft0, fa0, ft0
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; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fnmsub_h:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft0, fa0, ft0
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; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
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; RV64IZFH-NEXT: ret
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%a_ = fadd half 0.0, %a
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%nega = fneg half %a_
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%1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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define half @fnmsub_h_2(half %a, half %b, half %c) nounwind strictfp {
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; RV32IZFH-LABEL: fnmsub_h_2:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0
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; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fnmsub_h_2:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
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; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
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; RV64IZFH-NEXT: ret
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%b_ = fadd half 0.0, %b
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%negb = fneg half %b_
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%1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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