| .. |
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GlobalISel
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[RISCV] Reorder the vector register allocation order.
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2021-10-19 09:30:13 +08:00 |
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intrinsics
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…
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rvv
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[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
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2022-01-12 19:33:44 +00:00 |
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MachineSink-implicit-x0.mir
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Fix minor deficiency in machine-sink.
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2021-11-12 08:01:13 +01:00 |
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add-before-shl.ll
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[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
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2021-08-18 10:22:00 -07:00 |
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add-imm.ll
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[RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns.
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2021-08-18 11:07:11 -07:00 |
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addc-adde-sube-subc.ll
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…
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addcarry.ll
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…
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addimm-mulimm.ll
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[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
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2022-01-12 19:33:44 +00:00 |
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addrspacecast.ll
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[RISCV] Assume no-op addrspacecasts by default
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2020-12-18 21:03:37 +00:00 |
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aext-to-sext.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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align-loops.ll
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[CodeGen] Add -align-loops
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2021-08-04 12:45:18 -07:00 |
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align.ll
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…
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alloca.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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alu8.ll
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[RISCV] Generalize (srl (and X, 0xffff), C) -> (srli (slli X, (XLen-16), (XLen-16) + C) optimization.
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2022-01-09 23:37:10 -08:00 |
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alu16.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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alu32.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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alu64.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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analyze-branch.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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and.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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arith-with-overflow.ll
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…
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atomic-cmpxchg-flag.ll
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…
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atomic-cmpxchg.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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atomic-fence.ll
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…
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atomic-load-store.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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atomic-rmw.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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atomic-signext.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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attributes.ll
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[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
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2022-01-12 19:33:44 +00:00 |
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blockaddress.ll
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[RISCV] Fix inaccurate annotations on PseudoBRIND
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2020-08-21 11:38:42 +01:00 |
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branch-relaxation.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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branch.ll
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[RISCV] Add isel-patterns to optimize (a < 1) into blez (a <= 0)
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2021-03-15 11:32:43 -07:00 |
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bswap-ctlz-cttz-ctpop.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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byval.ll
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[RISCV] Reorder the vector register allocation order.
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2021-10-19 09:30:13 +08:00 |
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callee-saved-fpr32s.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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callee-saved-fpr64s.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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callee-saved-gprs.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-half.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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calling-conv-ilp32-ilp32f-common.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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calling-conv-ilp32.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-ilp32d.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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calling-conv-ilp32f-ilp32d-common.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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calling-conv-lp64-lp64f-common.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-lp64-lp64f-lp64d-common.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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calling-conv-lp64.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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calling-conv-rv32f-ilp32.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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calling-conv-sext-zext.ll
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[RISCV] Don't print zext.b alias.
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2021-01-05 10:41:08 -08:00 |
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calling-conv-vector-float.ll
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[RISCV] Fix a crash when lowering split float arguments
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2021-07-22 09:55:26 +01:00 |
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calls.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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cmp-bool.ll
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…
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codemodel-lowering.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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compress-float.ll
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[NFC][llvm] Inclusive language: reword uses of sanity test and check
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2021-11-25 07:21:42 -05:00 |
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compress-inline-asm.ll
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…
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compress.ll
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[NFC][llvm] Inclusive language: reword uses of sanity test and check
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2021-11-25 07:21:42 -05:00 |
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copy-frameindex.mir
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[RISCV] Reorder the vector register allocation order.
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2021-10-19 09:30:13 +08:00 |
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copysign-casts.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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disable-tail-calls.ll
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…
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disjoint.ll
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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div-by-constant.ll
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[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
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2022-01-12 19:33:44 +00:00 |
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div-pow2.ll
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[RISCV] Override TargetLowering::BuildSDIVPow2 to generate SELECT
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2022-01-11 15:54:35 +08:00 |
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div.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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double-arith-strict.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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double-arith.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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double-bitmanip-dagcombines.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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double-br-fcmp.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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double-calling-conv.ll
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[NFC][llvm] Inclusive language: reword uses of sanity test and check
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2021-11-25 07:21:42 -05:00 |
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double-convert-strict.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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double-convert.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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double-fcmp-strict.ll
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[RISCV] Add strictfp support for compares.
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2022-01-11 20:01:41 -08:00 |
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double-fcmp.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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double-frem.ll
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[RISCV] Promote f16 frem with Zfh.
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2021-11-10 17:35:07 -08:00 |
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double-imm.ll
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[RISCV] Use constant pool for large integers
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2021-12-31 14:48:48 +08:00 |
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double-intrinsics-strict.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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double-intrinsics.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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double-isnan.ll
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
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2020-12-10 09:15:52 -08:00 |
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double-mem.ll
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[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
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2021-07-20 09:22:06 -07:00 |
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double-previous-failure.ll
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[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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double-round-conv.ll
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[RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn)
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2022-01-11 09:05:57 -08:00 |
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double-select-fcmp.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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double-stack-spill-restore.ll
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[RISCV] Enable shrink wrap by default
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2021-09-02 09:47:58 -05:00 |
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dwarf-eh.ll
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…
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elf-preemption.ll
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[RISCV] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
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2021-05-11 11:29:45 -07:00 |
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exception-pointer-register.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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fastcc-float.ll
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[RISCV] Fix a crash when lowering split float arguments
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2021-07-22 09:55:26 +01:00 |
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fastcc-int.ll
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[RISCV] Reverse the order of loading/storing callee-saved registers.
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2021-11-22 23:02:11 +08:00 |
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fixups-diff.ll
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test: clean up some of the RISCV tests (NFC)
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2021-06-17 09:51:09 -07:00 |
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fixups-relax-diff.ll
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test: clean up some of the RISCV tests (NFC)
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2021-06-17 09:51:09 -07:00 |
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float-arith-strict.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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float-arith.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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float-bit-preserving-dagcombines.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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float-bitmanip-dagcombines.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
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2022-01-11 02:37:03 +00:00 |
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float-br-fcmp.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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float-convert-strict.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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float-convert.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
|
2022-01-10 09:08:29 -08:00 |
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float-fcmp-strict.ll
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[RISCV] Add strictfp support for compares.
|
2022-01-11 20:01:41 -08:00 |
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float-fcmp.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
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2022-01-10 09:08:29 -08:00 |
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float-frem.ll
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[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
|
2021-11-11 10:56:27 -08:00 |
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float-imm.ll
|
…
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|
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float-intrinsics-strict.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
|
2022-01-10 09:08:29 -08:00 |
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float-intrinsics.ll
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[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
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float-isnan.ll
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[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
|
2020-12-10 09:15:52 -08:00 |
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float-mem.ll
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[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
|
2021-07-20 09:22:06 -07:00 |
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float-round-conv.ll
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[RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn)
|
2022-01-11 09:05:57 -08:00 |
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float-select-fcmp.ll
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[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK lines. NFC
|
2022-01-10 09:08:29 -08:00 |
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flt-rounds.ll
|
[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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fold-addi-loadstore.ll
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[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
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fp-imm.ll
|
[RISCV] Generate pseudo instruction li
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2021-11-22 14:01:37 +08:00 |
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fp16-promote.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
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fp128.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
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fpclamptosat.ll
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[RISCV][LegalizeIntegerTypes] Teach PromoteSetCCOperands not to sext i32 comparisons for RV64 if the promoted values are already zero extended.
|
2021-12-31 17:15:20 -08:00 |
|
fpclamptosat_vec.ll
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[RISCV][LegalizeIntegerTypes] Teach PromoteSetCCOperands not to sext i32 comparisons for RV64 if the promoted values are already zero extended.
|
2021-12-31 17:15:20 -08:00 |
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fpenv.ll
|
[RISCV] Custom lowering of SET_ROUNDING
|
2021-04-22 15:04:55 +07:00 |
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frame-info.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
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frame.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
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frameaddr-returnaddr.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
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frm-dependency.ll
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[RISCV] Use AdjustInstrPostInstrSelection to insert a FRM dependency for scalar FP instructions with dynamic rounding mode.
|
2021-12-14 10:17:57 -08:00 |
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get-register-invalid.ll
|
…
|
|
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get-register-noreserve.ll
|
…
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|
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get-register-reserve.ll
|
…
|
|
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get-setcc-result-type.ll
|
…
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|
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ghccc-rv32.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
ghccc-rv64.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
half-arith-strict.ll
|
[RISCV] Add isel support for scalar STRICT_FADD/FSUB/FMUL/FDIV/FSQRT.
|
2021-12-14 10:50:55 -08:00 |
|
half-arith.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
half-bitmanip-dagcombines.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
half-br-fcmp.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
half-convert-strict.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
half-convert.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
half-fcmp-strict.ll
|
[RISCV] Add strictfp support for compares.
|
2022-01-11 20:01:41 -08:00 |
|
half-fcmp.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
half-frem.ll
|
[RISCV] Promote f16 frem with Zfh.
|
2021-11-10 17:35:07 -08:00 |
|
half-imm.ll
|
[RISCV] Support Zfh half-precision floating-point extension.
|
2020-12-03 09:16:33 +08:00 |
|
half-intrinsics.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
half-isnan.ll
|
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
|
2020-12-10 09:15:52 -08:00 |
|
half-mem.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
half-round-conv.ll
|
[RISCV] Add DAG combine to fold (fp_to_int (ffloor X)) -> (fcvt X, rdn)
|
2022-01-11 09:05:57 -08:00 |
|
half-select-fcmp.ll
|
[RISCV] Optimize select_cc after fp compare expansion
|
2021-01-14 13:41:40 -08:00 |
|
hoist-global-addr-base.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
i32-icmp.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
imm-cse.ll
|
…
|
|
|
imm.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
indirectbr.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
init-array.ll
|
…
|
|
|
inline-asm-S-constraint.ll
|
[RISCV] Support machine constraint "S"
|
2021-07-13 09:30:09 -07:00 |
|
inline-asm-abi-names.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
inline-asm-clobbers.ll
|
…
|
|
|
inline-asm-d-abi-names.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
inline-asm-d-constraint-f.ll
|
…
|
|
|
inline-asm-f-abi-names.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
inline-asm-f-constraint-f.ll
|
…
|
|
|
inline-asm-i-constraint-i1.ll
|
…
|
|
|
inline-asm-invalid.ll
|
[RISCV] Don't allow vector types to be used with inline asm 'r' constraint
|
2021-12-23 20:32:36 -06:00 |
|
inline-asm.ll
|
[RISCV] Don't advertise i32->i64 zextload as free for RV64.
|
2022-01-06 08:13:42 -08:00 |
|
interrupt-attr-args-error.ll
|
…
|
|
|
interrupt-attr-callee.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
interrupt-attr-invalid.ll
|
…
|
|
|
interrupt-attr-nocall.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
interrupt-attr-ret-error.ll
|
…
|
|
|
interrupt-attr.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
jumptable.ll
|
[RISCV] Generate 32 bits jumptable entries when code model is small
|
2022-01-11 18:20:37 +08:00 |
|
large-stack.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
legalize-fneg.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
lit.local.cfg
|
…
|
|
|
live-sp.mir
|
[RISCV] Fix invalid kill on callee save
|
2021-11-02 11:56:54 +00:00 |
|
lsr-legaladdimm.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
machine-outliner-patchable.ll
|
[MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL
|
2021-12-13 13:24:29 -08:00 |
|
machineoutliner-jumptable.mir
|
[RISCV] Fix Machine Outliner jump table handling.
|
2021-09-09 07:32:30 +02:00 |
|
machineoutliner.mir
|
…
|
|
|
mattr-invalid-combination.ll
|
…
|
|
|
mem.ll
|
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
|
mem64.ll
|
[RISCV][test] Add explicit dso_local to definitions in ELF static relocation model tests
|
2020-12-30 15:28:11 -08:00 |
|
mir-target-flags.ll
|
[TargetMachine] Don't imply dso_local on function declarations in Reloc::Static model for ELF/wasm
|
2020-12-05 14:54:37 -08:00 |
|
module-target-abi.ll
|
…
|
|
|
module-target-abi2.ll
|
…
|
|
|
mul.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
musttail-call.ll
|
OpaquePtr: Bulk update tests to use typed sret
|
2020-11-20 17:58:26 -05:00 |
|
neg-abs.ll
|
[RISCV][NFC] Increase test coverage of Zbt extension
|
2021-01-18 17:30:35 +00:00 |
|
nomerge.ll
|
…
|
|
|
option-nopic.ll
|
…
|
|
|
option-norelax.ll
|
…
|
|
|
option-norvc.ll
|
…
|
|
|
option-pic.ll
|
…
|
|
|
option-relax.ll
|
…
|
|
|
option-rvc.ll
|
…
|
|
|
optnone-store-no-combine.ll
|
[DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience
|
2021-12-23 10:48:28 +05:30 |
|
out-of-reach-emergency-slot.mir
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
overflow-intrinsic-optimizations.ll
|
[RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3()
|
2021-08-31 11:23:56 -07:00 |
|
patchable-function-entry.ll
|
Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases"
|
2021-05-29 15:11:37 +01:00 |
|
pic-models.ll
|
…
|
|
|
pr40333.ll
|
…
|
|
|
pr51206.ll
|
[RISCV] Use MULHU for more division by constant cases.
|
2021-12-09 09:10:14 -08:00 |
|
prefetch.ll
|
…
|
|
|
readcyclecounter.ll
|
…
|
|
|
rem.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
remat.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
reserved-reg-errors.ll
|
…
|
|
|
reserved-regs.ll
|
…
|
|
|
rotl-rotr.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
rv32e.ll
|
…
|
|
|
rv32i-rv64i-float-double.ll
|
[NFC][llvm] Inclusive language: reword uses of sanity test and check
|
2021-11-25 07:21:42 -05:00 |
|
rv32i-rv64i-half.ll
|
[NFC][llvm] Inclusive language: reword uses of sanity test and check
|
2021-11-25 07:21:42 -05:00 |
|
rv32zba.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
rv32zbb-intrinsic.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
rv32zbb-zbp.ll
|
[RISCV] Remove stale references to experimental-b. NFC
|
2022-01-12 12:13:21 -08:00 |
|
rv32zbb.ll
|
[RISCV] Remove stale references to experimental-b. NFC
|
2022-01-12 12:13:21 -08:00 |
|
rv32zbc-intrinsic.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
rv32zbe-intrinsic.ll
|
[RISCV] Remove experimental-b extension that includes all Zb* extensions
|
2021-10-07 20:47:17 -07:00 |
|
rv32zbf-intrinsic.ll
|
[RISCV] Add bfp and bfpw intrinsic in zbf extension
|
2022-01-13 02:53:00 +00:00 |
|
rv32zbp-intrinsic.ll
|
[RISCV] Remove experimental-b extension that includes all Zb* extensions
|
2021-10-07 20:47:17 -07:00 |
|
rv32zbp.ll
|
[RISCV] Remove stale references to experimental-b. NFC
|
2022-01-12 12:13:21 -08:00 |
|
rv32zbr.ll
|
[RISCV] Add IR intrinsic for Zbr extension
|
2021-04-02 10:58:45 -07:00 |
|
rv32zbs.ll
|
[RISCV] Remove stale references to experimental-b. NFC
|
2022-01-12 12:13:21 -08:00 |
|
rv32zbt.ll
|
[RISCV] Remove stale references to experimental-b. NFC
|
2022-01-12 12:13:21 -08:00 |
|
rv64-large-stack.ll
|
[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.
|
2021-07-20 09:22:06 -07:00 |
|
rv64d-double-convert-strict.ll
|
[RISCV] Support strict FP conversion operations.
|
2021-12-23 09:40:58 -06:00 |
|
rv64d-double-convert.ll
|
[RISCV] Custom lower (i32 (fptoui/fptosi X)).
|
2021-07-24 10:50:43 -07:00 |
|
rv64f-float-convert-strict.ll
|
[RISCV] Support strict FP conversion operations.
|
2021-12-23 09:40:58 -06:00 |
|
rv64f-float-convert.ll
|
[RISCV] Custom lower (i32 (fptoui/fptosi X)).
|
2021-07-24 10:50:43 -07:00 |
|
rv64i-complex-float.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
rv64i-demanded-bits.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
rv64i-double-softfloat.ll
|
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
|
2021-11-11 10:56:27 -08:00 |
|
rv64i-exhaustive-w-insts.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
rv64i-single-softfloat.ll
|
[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFC
|
2021-11-11 10:56:27 -08:00 |
|
rv64i-tricky-shifts.ll
|
…
|
|
|
rv64i-w-insts-legalization.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
rv64m-exhaustive-w-insts.ll
|
[RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits are used.
|
2021-08-18 10:22:00 -07:00 |
|
rv64m-w-insts-legalization.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
rv64zba.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
rv64zbb-intrinsic.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
rv64zbb-zbp.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
rv64zbb.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
rv64zbc-intrinsic.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
rv64zbe-intrinsic.ll
|
[RISCV] Remove experimental-b extension that includes all Zb* extensions
|
2021-10-07 20:47:17 -07:00 |
|
rv64zbf-intrinsic.ll
|
[RISCV] Add bfp and bfpw intrinsic in zbf extension
|
2022-01-13 02:53:00 +00:00 |
|
rv64zbp-intrinsic.ll
|
[RISCV] Remove experimental-b extension that includes all Zb* extensions
|
2021-10-07 20:47:17 -07:00 |
|
rv64zbp.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
rv64zbr.ll
|
[RISCV] Add IR intrinsic for Zbr extension
|
2021-04-02 10:58:45 -07:00 |
|
rv64zbs.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
rv64zbt.ll
|
[RISCV] Remove experimental-b extension that includes all Zb* extensions
|
2021-10-07 20:47:17 -07:00 |
|
rv64zfh-half-convert-strict.ll
|
[RISCV] Rename two tests to reflect extension being tested. NFC
|
2021-12-27 14:44:34 -08:00 |
|
rv64zfh-half-convert.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
rv64zfh-half-intrinsics-strict.ll
|
[RISCV] Add support for STRICT_LRINT/LLRINT/LROUND/LLROUND. Tests for other strict intrinsics.
|
2021-12-30 11:54:32 -08:00 |
|
rv64zfh-half-intrinsics.ll
|
[RISCV] Fix type in f16 and f64 version of lrint/llrint/lround/llround test cases. NFC
|
2021-12-27 14:59:23 -08:00 |
|
sadd_sat.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
sadd_sat_plus.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
saverestore.ll
|
[RISCV] Don't emit save-restore call if function is a interrupt handler
|
2021-04-16 12:54:47 +08:00 |
|
scalable-vector-struct.ll
|
[RISCV] Use whole register load/store for generic load/store.
|
2021-02-09 15:52:04 +08:00 |
|
sdata-limit-0.ll
|
…
|
|
|
sdata-limit-4.ll
|
…
|
|
|
sdata-limit-8.ll
|
…
|
|
|
sdata-local-sym.ll
|
…
|
|
|
select-and.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-bare.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
select-binop-identity.ll
|
[RISCV] Fold (add (select lhs, rhs, cc, 0, y), x) -> (select lhs, rhs, cc, x, (add x, y))
|
2021-08-10 09:02:56 -07:00 |
|
select-cc.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
select-const.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
select-constant-xor.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
select-optimize-multiple.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
select-optimize-multiple.mir
|
[RISCV] Reorder the vector register allocation order.
|
2021-10-19 09:30:13 +08:00 |
|
select-or.ll
|
Recommit "[RISCV] Legalize select when Zbt extension available"
|
2021-01-21 12:07:44 -08:00 |
|
selectcc-to-shiftand.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
setcc-logic.ll
|
[RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS.
|
2021-08-18 10:44:25 -07:00 |
|
sext-zext-trunc.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
sextw-removal.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
shadowcallstack.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
shift-and.ll
|
[RISCV] Add another isel optimization for (and (shl x, c2), c1)
|
2021-09-23 14:18:07 -07:00 |
|
shift-masked-shamt.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
shifts.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
shlimm-addimm.ll
|
[RISCV][test] Add tests of (add (shl r, c0), c1)
|
2021-10-14 14:53:03 +00:00 |
|
shrinkwrap.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
sink-icmp.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
spill-fpr-scalar.ll
|
[RISCV] Avoid using x0,x0 vsetvli for vmv.x.s and vfmv.f.s unless we know the sew/lmul ratio is constant.
|
2021-07-23 09:12:05 -07:00 |
|
split-offsets.ll
|
[RISCV] Add an MIR pass to replace redundant sext.w instructions with copies.
|
2022-01-06 08:23:42 -08:00 |
|
split-sp-adjust.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
srem-lkk.ll
|
[RISCV] Use constant pool for large integers
|
2021-12-31 14:48:48 +08:00 |
|
srem-seteq-illegal-types.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
srem-vector-lkk.ll
|
[RISCV] Use constant pool for large integers
|
2021-12-31 14:48:48 +08:00 |
|
ssub_sat.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
ssub_sat_plus.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
stack-realignment-with-variable-sized-objects.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
stack-realignment.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
stack-slot-size.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
stack-store-check.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
subtarget-features-std-ext.ll
|
…
|
|
|
tail-calls.ll
|
[RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.
|
2021-07-13 09:46:21 -07:00 |
|
target-abi-invalid.ll
|
…
|
|
|
target-abi-valid.ll
|
…
|
|
|
thread-pointer.ll
|
…
|
|
|
tls-models.ll
|
[RISCV][NFC] Regenerate RISCV CodeGen tests
|
2020-12-09 19:42:49 +00:00 |
|
uadd_sat.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
uadd_sat_plus.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
umulo-128-legalisation-lowering.ll
|
[RISCV] Reverse the order of loading/storing callee-saved registers.
|
2021-11-22 23:02:11 +08:00 |
|
unfold-masked-merge-scalar-variablemask.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
urem-lkk.ll
|
[RISCV] Use constant pool for large integers
|
2021-12-31 14:48:48 +08:00 |
|
urem-seteq-illegal-types.ll
|
[RISCV] Use shift for zero extension when Zbb and Zbp are not enabled
|
2022-01-11 02:37:03 +00:00 |
|
urem-vector-lkk.ll
|
[RISCV] Use constant pool for large integers
|
2021-12-31 14:48:48 +08:00 |
|
usub_sat.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
usub_sat_plus.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
vararg.ll
|
[RISCV] Use constant pool for large integers
|
2021-12-31 14:48:48 +08:00 |
|
vec3-setcc-crash.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
vector-abi.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
verify-instr.mir
|
…
|
|
|
wide-mem.ll
|
…
|
|
|
xaluo.ll
|
[RISCV] Update recently ratified Zb{a,b,c,s} extensions to no longer be experimental
|
2022-01-12 19:33:44 +00:00 |
|
zext-with-load-is-free.ll
|
[RISCV] Generate pseudo instruction li
|
2021-11-22 14:01:37 +08:00 |
|
zfh-half-intrinsics-strict.ll
|
[RISCV] Add support for STRICT_LRINT/LLRINT/LROUND/LLROUND. Tests for other strict intrinsics.
|
2021-12-30 11:54:32 -08:00 |
|
zfh-half-intrinsics.ll
|
[RISCV] Fix type in f16 and f64 version of lrint/llrint/lround/llround test cases. NFC
|
2021-12-27 14:59:23 -08:00 |
|
zfh-imm.ll
|
[RISCV] Support Zfh half-precision floating-point extension.
|
2020-12-03 09:16:33 +08:00 |
16877c5d2c