Andre Vieira 640527f7f1 [ARM] Fix assembly and disassembly for VMRS/VMSR ... Reviewed by: t.p.northover Differential Revision: https://reviews.llvm.org/D36306 llvm-svn: 313979		2017-09-22 12:17:42 +00:00
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AArch64	[AArch64] v8.3-a complex number support	2017-08-31 09:27:04 +00:00
AMDGPU	[AMDGPU][MC][GFX9] Added op_sel support for v_mad_*16, v_fma_f16, v_div_fixup_f16	2017-08-16 15:16:32 +00:00
ARC	[ARC] Add ARC backend.	2017-08-24 15:40:33 +00:00
ARM	[ARM] Fix assembly and disassembly for VMRS/VMSR	2017-09-22 12:17:42 +00:00
Hexagon	[Hexagon] Replace instruction definitions with auto-generated ones	2017-02-10 15:33:13 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	[mips] Implement the 'dext' aliases and it's disassembly alias.	2017-09-14 17:27:53 +00:00
PowerPC	[Power9] Add missing Power9 instructions.	2017-09-19 15:22:36 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Add support for IBM z14 processor (3/3)	2017-07-17 17:44:20 +00:00
X86	'into' instruction should not be decoded as a valid instr in 64-bit mode	2017-09-20 08:17:17 +00:00
XCore	…