forked from OSchip/llvm-project
c8e33c5ca1
This patch disables codegen support for branch likely instructions to address a potential bug. These branches were unselectable as they had the same patterns as the normal branches but came after them when ISel was concerned. The branch likely instructions were marked as having no delay slots when they have annulling delay slots. The delay slot filler does not currently handle annulling delay slot branches, so this would lead to wrong codegen if these branches were generated. Reviewers: atanasyan, nitesh.jain Differential Revision: https://reviews.llvm.org/D38169 llvm-svn: 314421 |
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AArch64 | ||
AMDGPU | ||
ARM | ||
AVR | ||
AsmParser | ||
BPF | ||
COFF | ||
Disassembler | ||
ELF | ||
Hexagon | ||
Lanai | ||
MachO | ||
Markup | ||
Mips | ||
PowerPC | ||
RISCV | ||
Sparc | ||
SystemZ | ||
WebAssembly | ||
X86 |