forked from OSchip/llvm-project
458 lines
18 KiB
ArmAsm
458 lines
18 KiB
ArmAsm
@ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
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@ RUN: not llvm-mc -triple=armv8 < %s 2> %t
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@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s
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@ Check for various assembly diagnostic messages on invalid input.
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@ 's' bit on an instruction that can't accept it.
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mlss r1, r2, r3, r4
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@ CHECK-ERRORS: error: instruction 'mls' can not set flags,
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@ CHECK-ERRORS: but 's' suffix specified
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@ Out of range shift immediate values.
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adc r1, r2, r3, lsl #invalid
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adc r4, r5, r6, lsl #-1
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adc r4, r5, r6, lsl #32
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adc r4, r5, r6, lsr #-1
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adc r4, r5, r6, lsr #33
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adc r4, r5, r6, asr #-1
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adc r4, r5, r6, asr #33
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adc r4, r5, r6, ror #-1
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adc r4, r5, r6, ror #32
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@ CHECK-ERRORS: error: invalid immediate shift value
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@ CHECK-ERRORS: adc r1, r2, r3, lsl #invalid
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, lsl #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, lsl #32
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, lsr #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, lsr #33
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, asr #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, asr #33
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, ror #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: adc r4, r5, r6, ror #32
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@ Out of range shift immediate values for load/store.
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str r1, [r2, r3, lsl #invalid]
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ldr r4, [r5], r6, lsl #-1
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pld r4, [r5, r6, lsl #32]
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str r4, [r5], r6, lsr #-1
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ldr r4, [r5, r6, lsr #33]
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pld r4, [r5, r6, asr #-1]
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str r4, [r5, r6, asr #33]
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ldr r4, [r5, r6, ror #-1]
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pld r4, [r5, r6, ror #32]
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pld r4, [r5, r6, rrx #0]
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@ CHECK-ERRORS: error: shift amount must be an immediate
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@ CHECK-ERRORS: str r1, [r2, r3, lsl #invalid]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: ldr r4, [r5], r6, lsl #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: pld r4, [r5, r6, lsl #32]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: str r4, [r5], r6, lsr #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: ldr r4, [r5, r6, lsr #33]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: pld r4, [r5, r6, asr #-1]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: str r4, [r5, r6, asr #33]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: ldr r4, [r5, r6, ror #-1]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate shift value out of range
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@ CHECK-ERRORS: pld r4, [r5, r6, ror #32]
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@ CHECK-ERRORS: error: ']' expected
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@ CHECK-ERRORS: pld r4, [r5, r6, rrx #0]
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@ Out of range 16-bit immediate on BKPT
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bkpt #65536
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ Out of range immediates for v8 HLT instruction.
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hlt #65536
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hlt #-1
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@CHECK-ERRORS-V8: error: invalid operand for instruction
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@CHECK-ERRORS-V8: hlt #65536
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@CHECK-ERRORS-V8: ^
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@CHECK-ERRORS-V8: error: invalid operand for instruction
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@CHECK-ERRORS-V8: hlt #-1
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@CHECK-ERRORS-V8: ^
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@ Illegal condition code for v8 HLT instruction.
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hlteq #2
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hltlt #23
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@CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified
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@CHECK-ERRORS-V8: hlteq #2
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@CHECK-ERRORS-V8: ^
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@CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified
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@CHECK-ERRORS-V8: hltlt #23
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@CHECK-ERRORS-V8: ^
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@ Out of range 4 and 3 bit immediates on CDP[2]
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@ Out of range immediates for CDP/CDP2
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cdp p7, #2, c1, c1, c1, #8
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cdp p7, #1, c1, c1, c1, #8
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cdp2 p7, #2, c1, c1, c1, #8
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cdp2 p7, #1, c1, c1, c1, #8
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ Out of range immediates for DBG
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dbg #-1
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dbg #16
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ Double-check that we're synced up with the right diagnostics.
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@ CHECK-ERRORS: dbg #16
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@ Out of range immediate for MCR/MCR2/MCRR/MCRR2
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mcr p7, #8, r5, c1, c1, #4
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mcr p7, #2, r5, c1, c1, #8
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mcr2 p7, #8, r5, c1, c1, #4
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mcr2 p7, #1, r5, c1, c1, #8
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mcrr p7, #16, r5, r4, c1
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mcrr2 p7, #16, r5, r4, c1
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ Out of range immediate for MOV
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movw r9, 0x10000
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ Invalid 's' bit usage for MOVW
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movs r6, #0xffff
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movwseq r9, #0xffff
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: instruction 'movw' can not set flags, but 's' suffix specified
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@ Out of range immediate for MOVT
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movt r9, 0x10000
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ Out of range immediates for MRC/MRC2/MRRC/MRRC2
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mrc p14, #8, r1, c1, c2, #4
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mrc p14, #1, r1, c1, c2, #8
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mrc2 p14, #8, r1, c1, c2, #4
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mrc2 p14, #0, r1, c1, c2, #9
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mrrc p7, #16, r5, r4, c1
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mrrc2 p7, #17, r5, r4, c1
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
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@ Shifter operand validation for PKH instructions.
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pkhbt r2, r2, r3, lsl #-1
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pkhbt r2, r2, r3, lsl #32
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pkhtb r2, r2, r3, asr #0
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pkhtb r2, r2, r3, asr #33
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pkhbt r2, r2, r3, asr #3
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pkhtb r2, r2, r3, lsl #3
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@ CHECK-ERRORS: error: immediate value out of range
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@ CHECK-ERRORS: pkhbt r2, r2, r3, lsl #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate value out of range
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@ CHECK-ERRORS: pkhbt r2, r2, r3, lsl #32
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate value out of range
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@ CHECK-ERRORS: pkhtb r2, r2, r3, asr #0
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: immediate value out of range
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@ CHECK-ERRORS: pkhtb r2, r2, r3, asr #33
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: lsl operand expected.
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@ CHECK-ERRORS: pkhbt r2, r2, r3, asr #3
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: asr operand expected.
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@ CHECK-ERRORS: pkhtb r2, r2, r3, lsl #3
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@ CHECK-ERRORS: ^
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@ bad values for SETEND
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setendne be
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setend me
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setend 1
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@ CHECK-ERRORS: error: instruction 'setend' is not predicable, but condition code specified
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@ CHECK-ERRORS: setendne be
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'be' or 'le' operand expected
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@ CHECK-ERRORS: setend me
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'be' or 'le' operand expected
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@ CHECK-ERRORS: setend 1
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@ CHECK-ERRORS: ^
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@ Out of range immediates and bad shift types for SSAT
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ssat r8, #0, r10, lsl #8
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ssat r8, #33, r10, lsl #8
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ssat r8, #1, r10, lsl #-1
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ssat r8, #1, r10, lsl #32
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ssat r8, #1, r10, asr #0
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ssat r8, #1, r10, asr #33
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ssat r8, #1, r10, lsr #5
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ssat r8, #1, r10, lsl fred
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ssat r8, #1, r10, lsl #fred
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: ssat r8, #0, r10, lsl #8
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: ssat r8, #33, r10, lsl #8
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'lsr' shift amount must be in range [0,31]
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@ CHECK-ERRORS: ssat r8, #1, r10, lsl #-1
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'lsr' shift amount must be in range [0,31]
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@ CHECK-ERRORS: ssat r8, #1, r10, lsl #32
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'asr' shift amount must be in range [1,32]
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@ CHECK-ERRORS: ssat r8, #1, r10, asr #0
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'asr' shift amount must be in range [1,32]
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@ CHECK-ERRORS: ssat r8, #1, r10, asr #33
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: shift operator 'asr' or 'lsl' expected
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@ CHECK-ERRORS: ssat r8, #1, r10, lsr #5
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: '#' expected
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@ CHECK-ERRORS: ssat r8, #1, r10, lsl fred
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: shift amount must be an immediate
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@ CHECK-ERRORS: ssat r8, #1, r10, lsl #fred
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@ CHECK-ERRORS: ^
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@ Out of range immediates for SSAT16
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ssat16 r2, #0, r7
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ssat16 r3, #17, r5
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: ssat16 r2, #0, r7
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: ssat16 r3, #17, r5
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@ CHECK-ERRORS: ^
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@ Out of order STM registers
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stmda sp!, {r5, r2}
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@ CHECK-ERRORS: warning: register list not in ascending order
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@ CHECK-ERRORS: stmda sp!, {r5, r2}
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@ CHECK-ERRORS: ^
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@ Out of range immediate on SVC
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svc #0x1000000
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: svc #0x1000000
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@ CHECK-ERRORS: ^
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@ Out of order Rt/Rt2 operands for ldrexd/strexd
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ldrexd r4, r3, [r8]
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strexd r6, r5, r3, [r8]
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@ CHECK-ERRORS: error: destination operands must be sequential
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@ CHECK-ERRORS: ldrexd r4, r3, [r8]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: source operands must be sequential
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@ CHECK-ERRORS: strexd r6, r5, r3, [r8]
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@ CHECK-ERRORS: ^
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@ Illegal rotate operators for extend instructions
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sxtb r8, r3, #8
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sxtb r8, r3, ror 24
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sxtb r8, r3, ror #8 -
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sxtab r3, r8, r3, ror #(fred - wilma)
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sxtab r7, r8, r3, ror #25
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sxtah r9, r3, r3, ror #-8
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sxtb16ge r2, r3, lsr #24
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: sxtb r8, r3, #8
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: '#' expected
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@ CHECK-ERRORS: sxtb r8, r3, ror 24
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: unknown token in expression
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@ CHECK-ERRORS: sxtb r8, r3, ror #8 -
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: malformed rotate expression
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@ CHECK-ERRORS: sxtb r8, r3, ror #8 -
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: rotate amount must be an immediate
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@ CHECK-ERRORS: sxtab r3, r8, r3, ror #(fred - wilma)
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24
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@ CHECK-ERRORS: sxtab r7, r8, r3, ror #25
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24
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@ CHECK-ERRORS: sxtah r9, r3, r3, ror #-8
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: sxtb16ge r2, r3, lsr #24
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@ CHECK-ERRORS: ^
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@ Out of range width for SBFX/UBFX
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sbfx r4, r5, #31, #2
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ubfxgt r4, r5, #16, #17
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@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb]
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@ CHECK-ERRORS: sbfx r4, r5, #31, #2
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb]
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@ CHECK-ERRORS: ubfxgt r4, r5, #16, #17
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@ CHECK-ERRORS: ^
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@ Out of order Rt/Rt2 operands for ldrd
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ldrd r4, r3, [r8]
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ldrd r4, r3, [r8, #8]!
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ldrd r4, r3, [r8], #8
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@ CHECK-ERRORS: error: destination operands must be sequential
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@ CHECK-ERRORS: ldrd r4, r3, [r8]
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: destination operands must be sequential
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@ CHECK-ERRORS: ldrd r4, r3, [r8, #8]!
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: destination operands must be sequential
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@ CHECK-ERRORS: ldrd r4, r3, [r8], #8
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@ CHECK-ERRORS: ^
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@ Bad register lists for VFP.
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vpush {s0, s3}
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@ CHECK-ERRORS: error: non-contiguous register range
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@ CHECK-ERRORS: vpush {s0, s3}
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@ CHECK-ERRORS: ^
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@ Out of range coprocessor option immediate.
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ldc2 p2, c8, [r1], { 256 }
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ldc2 p2, c8, [r1], { -1 }
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@ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255]
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@ CHECK-ERRORS: ldc2 p2, c8, [r1], { 256 }
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255]
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@ CHECK-ERRORS: ldc2 p2, c8, [r1], { -1 }
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@ CHECK-ERRORS: ^
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@ Bad CPS instruction format.
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cps f,#1
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: cps f,#1
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@ CHECK-ERRORS: ^
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@ Bad operands for msr
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msr #0, #0
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msr foo, #0
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: msr #0, #0
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: invalid operand for instruction
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@ CHECK-ERRORS: msr foo, #0
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@ CHECK-ERRORS: ^
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isb #-1
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isb #16
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@ CHECK-ERRORS: error: immediate value out of range
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@ CHECK-ERRORS: error: immediate value out of range
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nop.n
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@ CHECK-ERRORS: error: instruction with .n (narrow) qualifier not allowed in arm mode
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dmbeq #5
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dsble #15
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isblo #7
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@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified
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dmblt
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dsbne
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isbeq
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@ CHECK-ERRORS: error: instruction 'dmb' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'dsb' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'isb' is not predicable, but condition code specified
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mcr2le p7, #1, r5, c1, c1, #4
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mcrr2ne p7, #15, r5, r4, c1
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mrc2lo p14, #0, r1, c1, c2, #4
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mrrc2lo p7, #1, r5, r4, c1
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cdp2hi p10, #0, c6, c12, c0, #7
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@ CHECK-ERRORS: error: instruction 'mcr2' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'mcrr2' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'mrc2' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'mrrc2' is not predicable, but condition code specified
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@ CHECK-ERRORS: error: instruction 'cdp2' is not predicable, but condition code specified
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bkpteq #7
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@ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified
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ldm r2!, {r2, r3}
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ldmdb r2!, {r2, r3}
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ldmda r2!, {r2, r3}
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popeq {sp}
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@ CHECK-ERRORS: error: writeback register not allowed in register list
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@ CHECK-ERRORS: error: writeback register not allowed in register list
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@ CHECK-ERRORS: error: writeback register not allowed in register list
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@ CHECK-ERRORS: error: writeback register not allowed in register list
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vrintz.f32.f32 s0, s1
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vrintr.f32 s0, s1
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vrintx.f64.f64 d2, d5
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vrintz.f64 d10, d9
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vrinta.f32.f32 s6, s7
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vrintn.f32 s8, s9
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vrintp.f64.f64 d10, d11
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vrintm.f64 d12, d13
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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@ CHECK-ERRORS: error: instruction requires: FPARMv8
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