forked from OSchip/llvm-project
354 lines
11 KiB
LLVM
354 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse2 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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declare float @fmaxf(float, float)
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declare double @fmax(double, double)
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declare x86_fp80 @fmaxl(x86_fp80, x86_fp80)
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declare float @llvm.maxnum.f32(float, float)
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declare double @llvm.maxnum.f64(double, double)
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declare x86_fp80 @llvm.maxnum.f80(x86_fp80, x86_fp80)
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declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
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declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>)
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declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>)
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declare <4 x double> @llvm.maxnum.v4f64(<4 x double>, <4 x double>)
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declare <8 x double> @llvm.maxnum.v8f64(<8 x double>, <8 x double>)
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; FIXME: As the vector tests show, the SSE run shouldn't need this many moves.
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define float @test_fmaxf(float %x, float %y) {
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; SSE-LABEL: test_fmaxf:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm0, %xmm2
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; SSE-NEXT: cmpunordss %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm3
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: maxss %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm1, %xmm2
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; SSE-NEXT: orps %xmm3, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_fmaxf:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxss %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%z = call float @fmaxf(float %x, float %y) readnone
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ret float %z
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}
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define float @test_fmaxf_minsize(float %x, float %y) minsize {
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; CHECK-LABEL: test_fmaxf_minsize:
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; CHECK: # %bb.0:
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; CHECK-NEXT: jmp fmaxf # TAILCALL
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%z = call float @fmaxf(float %x, float %y) readnone
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ret float %z
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}
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; FIXME: As the vector tests show, the SSE run shouldn't need this many moves.
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define double @test_fmax(double %x, double %y) {
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; SSE-LABEL: test_fmax:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm0, %xmm2
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; SSE-NEXT: cmpunordsd %xmm0, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm3
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: maxsd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm1, %xmm2
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; SSE-NEXT: orpd %xmm3, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_fmax:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxsd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%z = call double @fmax(double %x, double %y) readnone
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ret double %z
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}
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define x86_fp80 @test_fmaxl(x86_fp80 %x, x86_fp80 %y) {
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; CHECK-LABEL: test_fmaxl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subq $40, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt (%rsp)
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; CHECK-NEXT: callq fmaxl
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; CHECK-NEXT: addq $40, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%z = call x86_fp80 @fmaxl(x86_fp80 %x, x86_fp80 %y) readnone
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ret x86_fp80 %z
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}
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define float @test_intrinsic_fmaxf(float %x, float %y) {
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; SSE-LABEL: test_intrinsic_fmaxf:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm0, %xmm2
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; SSE-NEXT: cmpunordss %xmm0, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm3
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: maxss %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm1, %xmm2
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; SSE-NEXT: orps %xmm3, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_intrinsic_fmaxf:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxss %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%z = call float @llvm.maxnum.f32(float %x, float %y) readnone
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ret float %z
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}
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define double @test_intrinsic_fmax(double %x, double %y) {
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; SSE-LABEL: test_intrinsic_fmax:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm0, %xmm2
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; SSE-NEXT: cmpunordsd %xmm0, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm3
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: maxsd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm1, %xmm2
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; SSE-NEXT: orpd %xmm3, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_intrinsic_fmax:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxsd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%z = call double @llvm.maxnum.f64(double %x, double %y) readnone
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ret double %z
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}
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define x86_fp80 @test_intrinsic_fmaxl(x86_fp80 %x, x86_fp80 %y) {
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; CHECK-LABEL: test_intrinsic_fmaxl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subq $40, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fldt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt {{[0-9]+}}(%rsp)
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; CHECK-NEXT: fstpt (%rsp)
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; CHECK-NEXT: callq fmaxl
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; CHECK-NEXT: addq $40, %rsp
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; CHECK-NEXT: .cfi_def_cfa_offset 8
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; CHECK-NEXT: retq
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%z = call x86_fp80 @llvm.maxnum.f80(x86_fp80 %x, x86_fp80 %y) readnone
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ret x86_fp80 %z
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}
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define <2 x float> @test_intrinsic_fmax_v2f32(<2 x float> %x, <2 x float> %y) {
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; SSE-LABEL: test_intrinsic_fmax_v2f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm2
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; SSE-NEXT: maxps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_intrinsic_fmax_v2f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxps %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%z = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %x, <2 x float> %y) readnone
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ret <2 x float> %z
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}
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define <4 x float> @test_intrinsic_fmax_v4f32(<4 x float> %x, <4 x float> %y) {
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; SSE-LABEL: test_intrinsic_fmax_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: movaps %xmm1, %xmm2
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; SSE-NEXT: maxps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_intrinsic_fmax_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxps %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%z = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %x, <4 x float> %y) readnone
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ret <4 x float> %z
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}
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define <2 x double> @test_intrinsic_fmax_v2f64(<2 x double> %x, <2 x double> %y) {
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; SSE-LABEL: test_intrinsic_fmax_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm1, %xmm2
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; SSE-NEXT: maxpd %xmm0, %xmm2
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_intrinsic_fmax_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxpd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%z = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %x, <2 x double> %y) readnone
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ret <2 x double> %z
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}
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define <4 x double> @test_intrinsic_fmax_v4f64(<4 x double> %x, <4 x double> %y) {
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; SSE-LABEL: test_intrinsic_fmax_v4f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm2, %xmm4
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; SSE-NEXT: maxpd %xmm0, %xmm4
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm2
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; SSE-NEXT: andnpd %xmm4, %xmm0
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; SSE-NEXT: orpd %xmm2, %xmm0
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; SSE-NEXT: movapd %xmm3, %xmm2
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; SSE-NEXT: maxpd %xmm1, %xmm2
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; SSE-NEXT: cmpunordpd %xmm1, %xmm1
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: andnpd %xmm2, %xmm1
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; SSE-NEXT: orpd %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_intrinsic_fmax_v4f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxpd %ymm0, %ymm1, %ymm2
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; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
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; AVX-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0
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; AVX-NEXT: retq
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%z = call <4 x double> @llvm.maxnum.v4f64(<4 x double> %x, <4 x double> %y) readnone
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ret <4 x double> %z
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}
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define <8 x double> @test_intrinsic_fmax_v8f64(<8 x double> %x, <8 x double> %y) {
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; SSE-LABEL: test_intrinsic_fmax_v8f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movapd %xmm4, %xmm8
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; SSE-NEXT: maxpd %xmm0, %xmm8
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm4
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; SSE-NEXT: andnpd %xmm8, %xmm0
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; SSE-NEXT: orpd %xmm4, %xmm0
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; SSE-NEXT: movapd %xmm5, %xmm4
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; SSE-NEXT: maxpd %xmm1, %xmm4
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; SSE-NEXT: cmpunordpd %xmm1, %xmm1
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; SSE-NEXT: andpd %xmm1, %xmm5
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; SSE-NEXT: andnpd %xmm4, %xmm1
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; SSE-NEXT: orpd %xmm5, %xmm1
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; SSE-NEXT: movapd %xmm6, %xmm4
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; SSE-NEXT: maxpd %xmm2, %xmm4
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; SSE-NEXT: cmpunordpd %xmm2, %xmm2
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; SSE-NEXT: andpd %xmm2, %xmm6
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; SSE-NEXT: andnpd %xmm4, %xmm2
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; SSE-NEXT: orpd %xmm6, %xmm2
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; SSE-NEXT: movapd %xmm7, %xmm4
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; SSE-NEXT: maxpd %xmm3, %xmm4
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; SSE-NEXT: cmpunordpd %xmm3, %xmm3
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; SSE-NEXT: andpd %xmm3, %xmm7
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; SSE-NEXT: andnpd %xmm4, %xmm3
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; SSE-NEXT: orpd %xmm7, %xmm3
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test_intrinsic_fmax_v8f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxpd %ymm0, %ymm2, %ymm4
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; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
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; AVX-NEXT: vblendvpd %ymm0, %ymm2, %ymm4, %ymm0
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; AVX-NEXT: vmaxpd %ymm1, %ymm3, %ymm2
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; AVX-NEXT: vcmpunordpd %ymm1, %ymm1, %ymm1
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; AVX-NEXT: vblendvpd %ymm1, %ymm3, %ymm2, %ymm1
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; AVX-NEXT: retq
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%z = call <8 x double> @llvm.maxnum.v8f64(<8 x double> %x, <8 x double> %y) readnone
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ret <8 x double> %z
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}
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; The IR-level FMF propagate to the node. With nnan, there's no need to blend.
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define double @maxnum_intrinsic_nnan_fmf_f64(double %a, double %b) {
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; SSE-LABEL: maxnum_intrinsic_nnan_fmf_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: maxsd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: maxnum_intrinsic_nnan_fmf_f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%r = tail call nnan double @llvm.maxnum.f64(double %a, double %b)
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ret double %r
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}
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; Make sure vectors work too.
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define <4 x float> @maxnum_intrinsic_nnan_fmf_f432(<4 x float> %a, <4 x float> %b) {
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; SSE-LABEL: maxnum_intrinsic_nnan_fmf_f432:
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; SSE: # %bb.0:
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; SSE-NEXT: maxps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: maxnum_intrinsic_nnan_fmf_f432:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%r = tail call nnan <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b)
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ret <4 x float> %r
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}
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; Current (but legacy someday): a function-level attribute should also enable the fold.
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define float @maxnum_intrinsic_nnan_attr_f32(float %a, float %b) #0 {
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; SSE-LABEL: maxnum_intrinsic_nnan_attr_f32:
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; SSE: # %bb.0:
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; SSE-NEXT: maxss %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: maxnum_intrinsic_nnan_attr_f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%r = tail call float @llvm.maxnum.f32(float %a, float %b)
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ret float %r
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}
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; Make sure vectors work too.
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define <2 x double> @maxnum_intrinsic_nnan_attr_f64(<2 x double> %a, <2 x double> %b) #0 {
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; SSE-LABEL: maxnum_intrinsic_nnan_attr_f64:
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; SSE: # %bb.0:
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; SSE-NEXT: maxpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: maxnum_intrinsic_nnan_attr_f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%r = tail call <2 x double> @llvm.maxnum.v2f64(<2 x double> %a, <2 x double> %b)
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ret <2 x double> %r
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}
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attributes #0 = { "no-nans-fp-math"="true" }
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