forked from OSchip/llvm-project
64 lines
3.5 KiB
LLVM
64 lines
3.5 KiB
LLVM
; FIXME: The si scheduler crashes if when lane mask tracking is enabled, so
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; we need to disable this when the si scheduler is being used.
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; The only way the subtarget knows that the si machine scheduler is being used
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; is to specify -mattr=si-scheduler. If we just pass --misched=si, the backend
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; won't know what scheduler we are using.
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; RUN: llc -march=amdgcn --misched=si -mattr=si-scheduler < %s | FileCheck %s
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; The test checks the "si" machine scheduler pass works correctly.
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; CHECK-LABEL: {{^}}main:
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; CHECK: s_wqm
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; CHECK: s_load_dwordx4
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; CHECK: s_load_dwordx8
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; CHECK: s_waitcnt lgkmcnt(0)
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; CHECK: image_sample
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; CHECK: s_waitcnt vmcnt(0)
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; CHECK: exp
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; CHECK: s_endpgm
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define amdgpu_ps void @main([6 x <16 x i8>] addrspace(4)* byval %arg, [17 x <16 x i8>] addrspace(4)* byval %arg1, [17 x <4 x i32>] addrspace(4)* byval %arg2, [34 x <8 x i32>] addrspace(4)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
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main_body:
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%tmp = bitcast [34 x <8 x i32>] addrspace(4)* %arg3 to <32 x i8> addrspace(4)*
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%tmp22 = load <32 x i8>, <32 x i8> addrspace(4)* %tmp, align 32, !tbaa !0
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%tmp23 = bitcast [17 x <4 x i32>] addrspace(4)* %arg2 to <16 x i8> addrspace(4)*
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%tmp24 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp23, align 16, !tbaa !0
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%i.i = extractelement <2 x i32> %arg11, i32 0
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%j.i = extractelement <2 x i32> %arg11, i32 1
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%i.f.i = bitcast i32 %i.i to float
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%j.f.i = bitcast i32 %j.i to float
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%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #1
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%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #1
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%i.i1 = extractelement <2 x i32> %arg11, i32 0
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%j.i2 = extractelement <2 x i32> %arg11, i32 1
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%i.f.i3 = bitcast i32 %i.i1 to float
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%j.f.i4 = bitcast i32 %j.i2 to float
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%p1.i5 = call float @llvm.amdgcn.interp.p1(float %i.f.i3, i32 1, i32 0, i32 %arg5) #1
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%p2.i6 = call float @llvm.amdgcn.interp.p2(float %p1.i5, float %j.f.i4, i32 1, i32 0, i32 %arg5) #1
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%tmp22.bc = bitcast <32 x i8> %tmp22 to <8 x i32>
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%tmp24.bc = bitcast <16 x i8> %tmp24 to <4 x i32>
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%tmp31 = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %p2.i, float %p2.i6, <8 x i32> %tmp22.bc, <4 x i32> %tmp24.bc, i1 0, i32 0, i32 0)
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%tmp32 = extractelement <4 x float> %tmp31, i32 0
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%tmp33 = extractelement <4 x float> %tmp31, i32 1
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%tmp34 = extractelement <4 x float> %tmp31, i32 2
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%tmp35 = extractelement <4 x float> %tmp31, i32 3
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%tmp36 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp32, float %tmp33)
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%tmp38 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp34, float %tmp35)
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call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp36, <2 x half> %tmp38, i1 true, i1 false) #0
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ret void
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}
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declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
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declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
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declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0
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declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
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declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind readonly }
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!0 = !{!1, !1, i64 0, i32 1}
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!1 = !{!"const", !2}
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!2 = !{!"tbaa root"}
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