forked from OSchip/llvm-project
112 lines
3.8 KiB
LLVM
112 lines
3.8 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
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; DAGCombiner will transform:
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; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
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; unless isFabsFree returns true
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; FUNC-LABEL: {{^}}s_fabs_fn_free:
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; R600-NOT: AND
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; R600: |PV.{{[XYZW]}}|
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; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff
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define amdgpu_kernel void @s_fabs_fn_free(float addrspace(1)* %out, i32 %in) {
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%bc= bitcast i32 %in to float
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%fabs = call float @fabs(float %bc)
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store float %fabs, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_fabs_free:
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; R600-NOT: AND
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; R600: |PV.{{[XYZW]}}|
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; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff
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define amdgpu_kernel void @s_fabs_free(float addrspace(1)* %out, i32 %in) {
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%bc= bitcast i32 %in to float
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%fabs = call float @llvm.fabs.f32(float %bc)
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store float %fabs, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_fabs_f32:
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7fffffff
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define amdgpu_kernel void @s_fabs_f32(float addrspace(1)* %out, float %in) {
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%fabs = call float @llvm.fabs.f32(float %in)
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store float %fabs, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_v2f32:
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; GCN: v_and_b32
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; GCN: v_and_b32
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define amdgpu_kernel void @fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
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store <2 x float> %fabs, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_v4f32:
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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; GCN: v_and_b32
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; GCN: v_and_b32
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; GCN: v_and_b32
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; GCN: v_and_b32
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define amdgpu_kernel void @fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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%fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
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store <4 x float> %fabs, <4 x float> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fabs_fn_fold:
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; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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; VI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
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; GCN-NOT: and
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; GCN: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
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define amdgpu_kernel void @fabs_fn_fold(float addrspace(1)* %out, float %in0, float %in1) {
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%fabs = call float @fabs(float %in0)
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%fmul = fmul float %fabs, %in1
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store float %fmul, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_fold:
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; SI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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; VI: s_load_dword [[ABS_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
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; GCN-NOT: and
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; GCN: v_mul_f32_e64 v{{[0-9]+}}, |[[ABS_VALUE]]|, v{{[0-9]+}}
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define amdgpu_kernel void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) {
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%fabs = call float @llvm.fabs.f32(float %in0)
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%fmul = fmul float %fabs, %in1
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store float %fmul, float addrspace(1)* %out
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ret void
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}
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; Make sure we turn some integer operations back into fabs
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; FUNC-LABEL: {{^}}bitpreserve_fabs_f32:
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; GCN: v_add_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|, 1.0
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define amdgpu_kernel void @bitpreserve_fabs_f32(float addrspace(1)* %out, float %in) {
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%in.bc = bitcast float %in to i32
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%int.abs = and i32 %in.bc, 2147483647
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%bc = bitcast i32 %int.abs to float
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%fadd = fadd float %bc, 1.0
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store float %fadd, float addrspace(1)* %out
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ret void
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}
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declare float @fabs(float) readnone
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declare float @llvm.fabs.f32(float) readnone
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declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
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