forked from OSchip/llvm-project
85 lines
2.9 KiB
LLVM
85 lines
2.9 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare i32 @llvm.amdgcn.workitem.id.x() readnone
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; SI-LABEL: {{^}}test_i64_vreg:
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; SI: v_add_i32
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; SI: v_addc_u32
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define amdgpu_kernel void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
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%a_ptr = getelementptr i64, i64 addrspace(1)* %inA, i32 %tid
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%b_ptr = getelementptr i64, i64 addrspace(1)* %inB, i32 %tid
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%a = load i64, i64 addrspace(1)* %a_ptr
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%b = load i64, i64 addrspace(1)* %b_ptr
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%result = add i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; Check that the SGPR add operand is correctly moved to a VGPR.
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; SI-LABEL: {{^}}sgpr_operand:
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; SI: s_add_u32
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; SI: s_addc_u32
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define amdgpu_kernel void @sgpr_operand(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 addrspace(1)* noalias %in_bar, i64 %a) {
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%foo = load i64, i64 addrspace(1)* %in, align 8
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%result = add i64 %foo, %a
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; Swap the arguments. Check that the SGPR -> VGPR copy works with the
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; SGPR as other operand.
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;
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; SI-LABEL: {{^}}sgpr_operand_reversed:
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; SI: s_add_u32
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; SI: s_addc_u32
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define amdgpu_kernel void @sgpr_operand_reversed(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %a) {
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%foo = load i64, i64 addrspace(1)* %in, align 8
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%result = add i64 %a, %foo
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}test_v2i64_sreg:
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; SI: s_add_u32
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; SI: s_addc_u32
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; SI: s_add_u32
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; SI: s_addc_u32
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define amdgpu_kernel void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, <2 x i64> %b) {
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%result = add <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}test_v2i64_vreg:
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; SI: v_add_i32
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; SI: v_addc_u32
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; SI: v_add_i32
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; SI: v_addc_u32
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define amdgpu_kernel void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() readnone
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%a_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inA, i32 %tid
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%b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inB, i32 %tid
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%a = load <2 x i64>, <2 x i64> addrspace(1)* %a_ptr
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%b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr
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%result = add <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}trunc_i64_add_to_i32:
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; SI: s_load_dword s[[SREG0:[0-9]+]]
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; SI: s_load_dword s[[SREG1:[0-9]+]]
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; SI: s_add_i32 [[SRESULT:s[0-9]+]], s[[SREG1]], s[[SREG0]]
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; SI-NOT: addc
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; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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; SI: buffer_store_dword [[VRESULT]],
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define amdgpu_kernel void @trunc_i64_add_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
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%add = add i64 %b, %a
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%trunc = trunc i64 %add to i32
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store i32 %trunc, i32 addrspace(1)* %out, align 8
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ret void
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}
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