forked from OSchip/llvm-project
103 lines
6.3 KiB
TableGen
103 lines
6.3 KiB
TableGen
//===--- HexagonIICHVX.td -------------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Though all these itinerary classes exist for V60 onwards, they are being
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// listed here as 'HVXV62Itin' because itinerary class description prior to V62
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// doesn't include operand cycle info. In future, I plan to merge them
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// together and call it 'HVXItin'.
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//
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class HVXV62Itin {
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list<InstrItinData> HVXV62Itin_list = [
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InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
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[InstrStage<1, [SLOT0, SLOT1]>],
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[3, 1, 1, 1]>,
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InstrItinData<COPROC_VX_vtc_long_SLOT23,
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[InstrStage<1, [SLOT2, SLOT3]>],
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[3, 1, 1, 1]>,
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InstrItinData<COPROC_VX_vtc_SLOT23,
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[InstrStage<1, [SLOT2, SLOT3]>],
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[3, 1, 1, 1]>,
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InstrItinData<CVI_VA, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLANE,CVI_SHIFT,
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CVI_MPY0, CVI_MPY1]>],
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[1, 1, 1, 1]>,
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InstrItinData<CVI_VA_DV, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF, CVI_MPY01]>],
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[1, 1, 1, 1]>,
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InstrItinData<CVI_VX_LONG, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1]>],
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[1, 1, 1, 1]>,
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InstrItinData<CVI_VX_LATE, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1]>],
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[1, 1, 1, 1]>,
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InstrItinData<CVI_VX, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY0, CVI_MPY1]>],
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[1, 1, 1, 1]>,
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InstrItinData<CVI_VX_DV_LONG, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VX_DV, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VX_DV_SLOT2, [InstrStage<1, [SLOT2], 0>,
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InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VX_DV_SLOT2_LONG_EARLY,
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[InstrStage<1, [SLOT2], 0>,
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InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VP, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VP_LONG, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VP_VS_EARLY, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VP_VS_LONG, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VP_VS, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VP_VS_LONG_EARLY,
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[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VP_DV, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VS, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_SHIFT]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VINLANESAT, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_XLANE, CVI_SHIFT,
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CVI_MPY0, CVI_MPY1]>],
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[1, 1, 1, 1]>,
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InstrItinData<CVI_VM_LD, [InstrStage<1, [SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_LD], 0>,
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InstrStage<1, [CVI_XLANE, CVI_SHIFT,
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CVI_MPY0, CVI_MPY1]>],
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[1, 1, 1, 1]>,
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InstrItinData<CVI_VM_TMP_LD, [InstrStage<1,[SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_LD]>],[1, 1, 1, 1, 10]>,
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InstrItinData<CVI_VM_CUR_LD, [InstrStage<1,[SLOT0, SLOT1], 0>,
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InstrStage<1, [CVI_LD], 0>,
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InstrStage<1, [CVI_XLANE, CVI_SHIFT,
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CVI_MPY0, CVI_MPY1]>],
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[1, 1, 1, 1]>,
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InstrItinData<CVI_VM_VP_LDU, [InstrStage<1,[SLOT0], 0>,
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InstrStage<1, [SLOT1], 0>,
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InstrStage<1, [CVI_LD], 0>,
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InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VM_ST, [InstrStage<1, [SLOT0], 0>,
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InstrStage<1, [CVI_ST], 0>,
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InstrStage<1, [CVI_XLANE, CVI_SHIFT,
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CVI_MPY0, CVI_MPY1]>],
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[1, 1, 1, 1]>,
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InstrItinData<CVI_VM_NEW_ST, [InstrStage<1,[SLOT0], 0>,
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InstrStage<1, [CVI_ST]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_VM_STU, [InstrStage<1, [SLOT0], 0>,
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InstrStage<1, [SLOT1], 0>,
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InstrStage<1, [CVI_ST], 0>,
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InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>,
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InstrItinData<CVI_HIST, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
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InstrStage<1, [CVI_ALL]>], [1, 1, 1, 1]>];
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}
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