forked from OSchip/llvm-project
104 lines
4.0 KiB
C++
104 lines
4.0 KiB
C++
//=- HexagonFrameLowering.h - Define frame lowering for Hexagon --*- C++ -*--=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H
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#include "Hexagon.h"
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#include "llvm/Target/TargetFrameLowering.h"
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namespace llvm {
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class HexagonInstrInfo;
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class HexagonRegisterInfo;
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class HexagonFrameLowering : public TargetFrameLowering {
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public:
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explicit HexagonFrameLowering()
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: TargetFrameLowering(StackGrowsDown, 8, 0, 1, true) {}
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// All of the prolog/epilog functionality, including saving and restoring
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// callee-saved registers is handled in emitPrologue. This is to have the
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// logic for shrink-wrapping in one place.
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void emitPrologue(MachineFunction &MF) const override;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
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override {}
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const override {
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return true;
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}
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bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const override {
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return true;
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}
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *RS = nullptr) const override;
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void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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RegScavenger *RS) const override;
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bool targetHandlesStackFrameRounding() const override {
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return true;
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}
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int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
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bool hasFP(const MachineFunction &MF) const override;
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const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries)
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const override {
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static const SpillSlot Offsets[] = {
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{ Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 },
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{ Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 },
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{ Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 },
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{ Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 },
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{ Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
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{ Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 }
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};
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NumEntries = array_lengthof(Offsets);
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return Offsets;
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}
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bool assignCalleeSavedSpillSlots(MachineFunction &MF,
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const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
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const override;
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bool needsAligna(const MachineFunction &MF) const;
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MachineInstr *getAlignaInstr(MachineFunction &MF) const;
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private:
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typedef std::vector<CalleeSavedInfo> CSIVect;
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void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
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unsigned SP, unsigned CF) const;
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void insertPrologueInBlock(MachineBasicBlock &MBB) const;
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void insertEpilogueInBlock(MachineBasicBlock &MBB) const;
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bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
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const HexagonRegisterInfo &HRI) const;
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bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI,
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const HexagonRegisterInfo &HRI) const;
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void adjustForCalleeSavedRegsSpillCall(MachineFunction &MF) const;
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bool replacePredRegPseudoSpillCode(MachineFunction &MF) const;
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bool replaceVecPredRegPseudoSpillCode(MachineFunction &MF) const;
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void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB,
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MachineBasicBlock *&EpilogB) const;
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bool shouldInlineCSR(llvm::MachineFunction&, const CSIVect&) const;
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bool useSpillFunction(MachineFunction &MF, const CSIVect &CSI) const;
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bool useRestoreFunction(MachineFunction &MF, const CSIVect &CSI) const;
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};
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} // End llvm namespace
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#endif
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