forked from OSchip/llvm-project
67 lines
2.9 KiB
LLVM
67 lines
2.9 KiB
LLVM
; RUN: opt %loadPolly -polly-scops -analyze < %s | FileCheck %s
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; RUN: opt %loadPolly -polly-function-scops -analyze < %s | FileCheck %s
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; void f(long a[][128], long N, long M) {
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; long i, j;
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; for (j = 0; j < (4*N + 7*M +3); ++j)
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; for (i = 0; i < (5*N + 2); ++i)
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; a[j][i] = 0
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; }
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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define void @f([128 x i64]* nocapture %a, i64 %N, i64 %M) nounwind {
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entry:
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%0 = shl i64 %N, 2 ; <i64> [#uses=2]
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%1 = mul i64 %M, 7 ; <i64> [#uses=2]
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%2 = or i64 %0, 3 ; <i64> [#uses=1]
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%3 = add nsw i64 %2, %1 ; <i64> [#uses=1]
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%4 = icmp sgt i64 %3, 0 ; <i1> [#uses=1]
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br i1 %4, label %bb.nph8, label %return
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bb1: ; preds = %bb2.preheader, %bb1
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%i.06 = phi i64 [ 0, %bb2.preheader ], [ %5, %bb1 ] ; <i64> [#uses=2]
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%scevgep = getelementptr [128 x i64], [128 x i64]* %a, i64 %i.06, i64 %10 ; <i64*> [#uses=1]
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store i64 0, i64* %scevgep, align 8
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%5 = add nsw i64 %i.06, 1 ; <i64> [#uses=2]
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%exitcond = icmp eq i64 %5, %8 ; <i1> [#uses=1]
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br i1 %exitcond, label %bb3, label %bb1
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bb3: ; preds = %bb1
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%6 = add i64 %10, 1 ; <i64> [#uses=2]
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%exitcond14 = icmp eq i64 %6, %tmp13 ; <i1> [#uses=1]
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br i1 %exitcond14, label %return, label %bb2.preheader
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bb.nph8: ; preds = %entry
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%7 = mul i64 %N, 5 ; <i64> [#uses=1]
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%8 = add nsw i64 %7, 2 ; <i64> [#uses=2]
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%9 = icmp sgt i64 %8, 0 ; <i1> [#uses=1]
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br i1 %9, label %bb.nph8.split, label %return
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bb.nph8.split: ; preds = %bb.nph8
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%tmp12 = add i64 %1, %0 ; <i64> [#uses=1]
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%tmp13 = add i64 %tmp12, 3 ; <i64> [#uses=1]
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br label %bb2.preheader
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bb2.preheader: ; preds = %bb.nph8.split, %bb3
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%10 = phi i64 [ 0, %bb.nph8.split ], [ %6, %bb3 ] ; <i64> [#uses=2]
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br label %bb1
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return: ; preds = %bb.nph8, %bb3, %entry
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ret void
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}
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; CHECK: p0: %N
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; CHECK-NEXT: p1: %M
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;
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; CHECK: Statements {
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; CHECK-NEXT: Stmt_bb1
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; CHECK-NEXT: Domain :=
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; CHECK-NEXT: [N, M] -> { Stmt_bb1[i0, i1] : 0 <= i0 <= 2 + 4N + 7M and 0 <= i1 <= 1 + 5N };
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; CHECK-NEXT: Schedule :=
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; CHECK-NEXT: [N, M] -> { Stmt_bb1[i0, i1] -> [i0, i1] };
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; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [N, M] -> { Stmt_bb1[i0, i1] -> MemRef_a[i1, i0] };
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; CHECK-NEXT: }
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