forked from OSchip/llvm-project
121 lines
5.6 KiB
C
121 lines
5.6 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// REQUIRES: powerpc-registered-target
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// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
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// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
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// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
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// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_add(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
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// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw add i32* [[A_ADDR]], i32 [[TMP1]] monotonic, align 4
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_add(int a, int b) {
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__fetch_and_add(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_addlp(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
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// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw add i64* [[A_ADDR]], i64 [[TMP1]] monotonic, align 8
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_addlp(long a, long b) {
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__fetch_and_addlp(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_and(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
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// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw and i32* [[A_ADDR]], i32 [[TMP1]] monotonic, align 4
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_and(unsigned int a, unsigned int b) {
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__fetch_and_and(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_andlp(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
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// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw and i64* [[A_ADDR]], i64 [[TMP1]] monotonic, align 8
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
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__fetch_and_andlp(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_or(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
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// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw or i32* [[A_ADDR]], i32 [[TMP1]] monotonic, align 4
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_or(unsigned int a, unsigned int b) {
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__fetch_and_or(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_orlp(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
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// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw or i64* [[A_ADDR]], i64 [[TMP1]] monotonic, align 8
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
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__fetch_and_orlp(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_swap(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
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// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw xchg i32* [[A_ADDR]], i32 [[TMP1]] monotonic, align 4
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_swap(unsigned int a, unsigned int b) {
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__fetch_and_swap(&a, b);
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}
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// CHECK-LABEL: @test_builtin_ppc_fetch_and_swaplp(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
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// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[B_ADDR]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw xchg i64* [[A_ADDR]], i64 [[TMP1]] monotonic, align 8
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// CHECK-NEXT: ret void
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//
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void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {
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__fetch_and_swaplp(&a, b);
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}
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