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AArch64
[Aarch64] Correct register class for pseudo instructions
2021-09-09 14:31:49 -04:00
AMDGPU
[AMDGPU] Make fexp.ll test autogenerated
2021-09-09 15:37:28 -04:00
ARC
[ARC] Add codegen for the readcyclecounter intrinsic along with disassembly for associated instructions
2021-08-24 11:53:20 -07:00
ARM
Port the cost model printer to New PM
2021-09-08 14:47:05 -07:00
AVR
[AVR] emit 'MCSA_Global' references to '__do_global_ctors' and '__do_global_dtors'
2021-08-05 10:37:36 +08:00
BPF
[BPF] support btf_tag attribute in .BTF section
2021-08-28 21:02:27 -07:00
Generic
Moved the test to X86 as it's x86 specific.
2021-08-31 14:48:29 -04:00
Hexagon
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Inputs
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Lanai
[Lanai] fix lowering wide returns
2021-08-05 21:08:09 -07:00
M68k
[M68k][test] Migrate the remaining fixup and relaxation tests
2021-09-04 16:27:13 -07:00
MIR
The maximal representable alignment in LLVM IR is 1GiB, not 512MiB
2021-08-26 12:53:39 +03:00
MSP430
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Mips
[MipsISelLowering] avoid emitting libcalls to __multi3
2021-09-02 10:41:37 -07:00
NVPTX
[NVPTX] Simplify and generalize constant printer.
2021-09-09 11:30:19 -07:00
PowerPC
[DAG] Fix GT -> GE condition when creating SetCC
2021-09-08 12:41:51 +01:00
RISCV
[RISCV] Add test cases showing failure to fold splatted shift amounts across basic blocks.
2021-09-09 12:45:30 -07:00
SPARC
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SystemZ
SystemZ: Tidy up a mir test
2021-08-10 13:56:54 -04:00
Thumb
[ARM] Implement target hook function to decide folding (mul (add x, c1), c2)
2021-09-07 15:42:43 +08:00
Thumb2
[SimplifyCFG] performBranchToCommonDestFolding(): require block-closed SSA form for bonus instructions (PR51125)
2021-09-09 12:28:09 +03:00
VE
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WebAssembly
[WebAssembly][test] Fix lower-em-sjlj-indirect-setjmp.ll after D109375
2021-09-08 00:21:30 -07:00
WinCFGuard
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WinEH
Fix SEH table addresses for Windows
2021-08-20 22:32:12 +03:00
X86
[X86] Disable muloti4 libcalls for x86-64.
2021-09-09 10:03:15 -07:00
XCore
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