forked from OSchip/llvm-project
31 lines
1.3 KiB
LLVM
31 lines
1.3 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s
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; REQUIRES: asserts
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; Test that the accessSize is set on a post-increment store. If not, an assert
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; is triggered in getBaseAndOffset()
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%struct.A = type { i8, i32, i32, i32, [10 x i32], [10 x i32], [80 x i32], [80 x i32], [8 x i32], i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 }
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; Function Attrs: nounwind
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define fastcc void @Decoder_amr(i8 zeroext %mode) #0 {
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entry:
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br label %for.cond64.preheader.i
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for.cond64.preheader.i:
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%i.1984.i = phi i32 [ 0, %entry ], [ %inc166.i.1, %for.cond64.preheader.i ]
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%inc166.i = add nsw i32 %i.1984.i, 1
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%arrayidx71.i1422.1 = getelementptr inbounds %struct.A, %struct.A* undef, i32 0, i32 7, i32 %inc166.i
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%storemerge800.i.1 = select i1 undef, i32 1310, i32 undef
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%sub156.i.1 = sub nsw i32 0, %storemerge800.i.1
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%sub156.storemerge800.i.1 = select i1 undef, i32 %storemerge800.i.1, i32 %sub156.i.1
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store i32 %sub156.storemerge800.i.1, i32* %arrayidx71.i1422.1, align 4
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store i32 0, i32* undef, align 4
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%inc166.i.1 = add nsw i32 %i.1984.i, 2
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br label %for.cond64.preheader.i
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if.end:
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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