forked from OSchip/llvm-project
131 lines
3.9 KiB
C++
131 lines
3.9 KiB
C++
//===-- AVRTargetMachine.cpp - Define TargetMachine for AVR ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the AVR specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "AVRTargetMachine.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "AVR.h"
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#include "AVRTargetObjectFile.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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namespace llvm {
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static const char *AVRDataLayout = "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8";
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/// Processes a CPU name.
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static StringRef getCPU(StringRef CPU) {
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if (CPU.empty() || CPU == "generic") {
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return "avr2";
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}
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return CPU;
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}
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static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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return RM.hasValue() ? *RM : Reloc::Static;
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}
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static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
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if (CM)
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return *CM;
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return CodeModel::Small;
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}
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AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options,
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getEffectiveRelocModel(RM), getEffectiveCodeModel(CM),
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OL),
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SubTarget(TT, getCPU(CPU), FS, *this) {
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this->TLOF = make_unique<AVRTargetObjectFile>();
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initAsmInfo();
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}
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namespace {
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/// AVR Code Generator Pass Configuration Options.
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class AVRPassConfig : public TargetPassConfig {
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public:
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AVRPassConfig(AVRTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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AVRTargetMachine &getAVRTargetMachine() const {
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return getTM<AVRTargetMachine>();
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}
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bool addInstSelector() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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void addPreRegAlloc() override;
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};
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} // namespace
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TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new AVRPassConfig(*this, PM);
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}
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extern "C" void LLVMInitializeAVRTarget() {
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// Register the target.
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RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget());
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auto &PR = *PassRegistry::getPassRegistry();
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initializeAVRExpandPseudoPass(PR);
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initializeAVRRelaxMemPass(PR);
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}
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const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
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return &SubTarget;
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}
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const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
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return &SubTarget;
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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bool AVRPassConfig::addInstSelector() {
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// Install an instruction selector.
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addPass(createAVRISelDag(getAVRTargetMachine(), getOptLevel()));
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// Create the frame analyzer pass used by the PEI pass.
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addPass(createAVRFrameAnalyzerPass());
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return false;
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}
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void AVRPassConfig::addPreRegAlloc() {
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// Create the dynalloc SP save/restore pass to handle variable sized allocas.
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addPass(createAVRDynAllocaSRPass());
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}
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void AVRPassConfig::addPreSched2() {
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addPass(createAVRRelaxMemPass());
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addPass(createAVRExpandPseudoPass());
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}
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void AVRPassConfig::addPreEmitPass() {
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// Must run branch selection immediately preceding the asm printer.
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addPass(&BranchRelaxationPassID);
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}
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} // end of namespace llvm
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