forked from OSchip/llvm-project
167 lines
5.5 KiB
C++
167 lines
5.5 KiB
C++
//===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AArch64 specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64Subtarget.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64PBQPRegAlloc.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-subtarget"
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#define GET_SUBTARGETINFO_CTOR
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#define GET_SUBTARGETINFO_TARGET_DESC
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#include "AArch64GenSubtargetInfo.inc"
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static cl::opt<bool>
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EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
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"converter pass"), cl::init(true), cl::Hidden);
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// If OS supports TBI, use this flag to enable it.
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static cl::opt<bool>
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UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
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"an address is ignored"), cl::init(false), cl::Hidden);
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AArch64Subtarget &
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AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
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// Determine default and user-specified characteristics
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if (CPUString.empty())
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CPUString = "generic";
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ParseSubtargetFeatures(CPUString, FS);
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initializeProperties();
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return *this;
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}
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void AArch64Subtarget::initializeProperties() {
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// Initialize CPU specific properties. We should add a tablegen feature for
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// this in the future so we can specify it together with the subtarget
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// features.
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switch (ARMProcFamily) {
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case Cyclone:
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CacheLineSize = 64;
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PrefetchDistance = 280;
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MinPrefetchStride = 2048;
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MaxPrefetchIterationsAhead = 3;
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break;
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case CortexA57:
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MaxInterleaveFactor = 4;
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break;
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case ExynosM1:
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PrefFunctionAlignment = 4;
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PrefLoopAlignment = 3;
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break;
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case Kryo:
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MaxInterleaveFactor = 4;
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VectorInsertExtractBaseCost = 2;
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break;
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case CortexA35: break;
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case CortexA53: break;
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case Others: break;
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}
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}
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AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS,
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const TargetMachine &TM, bool LittleEndian)
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: AArch64GenSubtargetInfo(TT, CPU, FS), ReserveX18(TT.isOSDarwin()),
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IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(),
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InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
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TLInfo(TM, *this), GISel() {}
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const CallLowering *AArch64Subtarget::getCallLowering() const {
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assert(GISel && "Access to GlobalISel APIs not set");
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return GISel->getCallLowering();
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}
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const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
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assert(GISel && "Access to GlobalISel APIs not set");
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return GISel->getRegBankInfo();
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}
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/// Find the target operand flags that describe how a global value should be
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/// referenced for the current subtarget.
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unsigned char
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AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
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const TargetMachine &TM) const {
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// MachO large model always goes via a GOT, simply to get a single 8-byte
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// absolute relocation on all global addresses.
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if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
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return AArch64II::MO_GOT;
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Reloc::Model RM = TM.getRelocationModel();
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if (!shouldAssumeDSOLocal(RM, TargetTriple, *GV->getParent(), GV))
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return AArch64II::MO_GOT;
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// The small code mode's direct accesses use ADRP, which cannot necessarily
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// produce the value 0 (if the code is above 4GB).
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if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage())
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return AArch64II::MO_GOT;
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return AArch64II::MO_NO_FLAG;
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}
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/// This function returns the name of a function which has an interface
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/// like the non-standard bzero function, if such a function exists on
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/// the current subtarget and it is considered prefereable over
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/// memset with zero passed as the second argument. Otherwise it
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/// returns null.
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const char *AArch64Subtarget::getBZeroEntry() const {
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// Prefer bzero on Darwin only.
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if(isTargetDarwin())
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return "bzero";
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return nullptr;
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}
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void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
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MachineInstr *begin, MachineInstr *end,
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unsigned NumRegionInstrs) const {
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// LNT run (at least on Cyclone) showed reasonably significant gains for
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// bi-directional scheduling. 253.perlbmk.
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Policy.OnlyTopDown = false;
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Policy.OnlyBottomUp = false;
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// Enabling or Disabling the latency heuristic is a close call: It seems to
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// help nearly no benchmark on out-of-order architectures, on the other hand
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// it regresses register pressure on a few benchmarking.
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Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
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}
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bool AArch64Subtarget::enableEarlyIfConversion() const {
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return EnableEarlyIfConvert;
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}
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bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
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if (!UseAddressTopByteIgnored)
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return false;
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if (TargetTriple.isiOS()) {
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unsigned Major, Minor, Micro;
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TargetTriple.getiOSVersion(Major, Minor, Micro);
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return Major >= 8;
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}
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return false;
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}
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std::unique_ptr<PBQPRAConstraint>
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AArch64Subtarget::getCustomPBQPConstraints() const {
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return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;
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}
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