forked from OSchip/llvm-project
7218032019
Summary: We were canonizalizing the pre loop (into loop-simplify form) before the post loop blocks were added into parent loop. This is incorrect when IRCE is done on a subloop. The post-loop blocks are created, but not yet added to the parent loop. So, loop-simplification on the pre-loop incorrectly updates LoopInfo. This patch corrects the ordering so that pre and post loop blocks are added to parent loop (if any), and then the loops are canonicalized to LCSSA and LoopSimplifyForm. Reviewers: reames, sanjoy, apilipenko Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33846 llvm-svn: 304800 |
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| .. | ||
| add-metadata-pre-post-loops.ll | ||
| bad-loop-structure.ll | ||
| bug-loop-varying-upper-limit.ll | ||
| bug-mismatched-types.ll | ||
| conjunctive-checks.ll | ||
| correct-loop-info.ll | ||
| decrementing-loop.ll | ||
| low-becount.ll | ||
| multiple-access-no-preloop.ll | ||
| not-likely-taken.ll | ||
| only-lower-check.ll | ||
| only-upper-check.ll | ||
| single-access-no-preloop.ll | ||
| single-access-with-preloop.ll | ||
| skip-profitability-checks.ll | ||
| unhandled.ll | ||
| with-parent-loops.ll | ||