llvm-project/llvm/lib/Target/Sparc
Matthias Braun 941a705b7b MachineFunction: Return reference for getFrameInfo(); NFC
getFrameInfo() never returns nullptr so we should use a reference
instead of a pointer.

llvm-svn: 277017
2016-07-28 18:40:00 +00:00
..
AsmParser Don't pass a Reloc::Model to MC. 2016-05-18 11:58:50 +00:00
Disassembler This change adds co-processor condition branching and conditional traps to the Sparc back-end. 2016-03-09 18:20:21 +00:00
InstPrinter Prune some includes from headers and sink some inline functions 2016-06-22 23:23:08 +00:00
MCTargetDesc MC] Provide an MCTargetOptions to implementors of MCAsmBackendCtorTy, NFC 2016-07-25 17:18:28 +00:00
TargetInfo Remove autoconf support 2016-01-26 21:29:08 +00:00
CMakeLists.txt [Sparc][LEON] LEON Erratum fix. Insert NOP after LD or LDF instruction. 2016-05-23 10:56:36 +00:00
DelaySlotFiller.cpp [SPARC] Additional condition required for DelaySlot fixing erratum in revision r273108. 2016-06-19 12:56:42 +00:00
LLVMBuild.txt
LeonFeatures.td [Sparc] Leon errata fix passes. 2016-07-08 15:33:56 +00:00
LeonPasses.cpp [Sparc] Leon errata fix passes. 2016-07-08 15:33:56 +00:00
LeonPasses.h [Sparc] Leon errata fix passes. 2016-07-08 15:33:56 +00:00
README.txt Initial test commit only 2016-02-26 11:38:24 +00:00
Sparc.h This change adds co-processor condition branching and conditional traps to the Sparc back-end. 2016-03-09 18:20:21 +00:00
Sparc.td [Sparc] Leon errata fix passes. 2016-07-08 15:33:56 +00:00
SparcAsmPrinter.cpp Use isPositionIndependent(). NFC. 2016-06-27 18:37:44 +00:00
SparcCallingConv.td [Sparc] Implement i64 load/store support for 32-bit sparc. 2015-08-10 19:11:39 +00:00
SparcFrameLowering.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
SparcFrameLowering.h Change eliminateCallFramePseudoInstr() to return an iterator 2016-03-31 18:33:38 +00:00
SparcISelDAGToDAG.cpp [Sparc] Enable more inline assembly constraints. 2016-05-20 09:03:01 +00:00
SparcISelLowering.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
SparcISelLowering.h CodeGen: Use MachineInstr& in TargetLowering, NFC 2016-06-30 22:52:52 +00:00
SparcInstr64Bit.td [SPARC] Fix 8 and 16-bit atomic load and store. 2016-05-23 20:33:00 +00:00
SparcInstrAliases.td This change adds co-processor condition branching and conditional traps to the Sparc back-end. 2016-03-09 18:20:21 +00:00
SparcInstrFormats.td [Sparc] This provides support for itineraries on Sparc. 2016-04-22 08:17:17 +00:00
SparcInstrInfo.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
SparcInstrInfo.h Rename AnalyzeBranch* to analyzeBranch*. 2016-07-15 14:41:04 +00:00
SparcInstrInfo.td [SPARC] Fixes for hardware errata on LEON processor. 2016-06-19 11:03:28 +00:00
SparcInstrVIS.td
SparcMCInstLower.cpp [NFC] Header cleanup 2016-04-18 09:17:29 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcRegisterInfo.cpp Pass DebugLoc and SDLoc by const ref. 2016-06-12 15:39:02 +00:00
SparcRegisterInfo.h [sparc] Remove some unused (and undefined) declarations. 2016-05-27 10:19:03 +00:00
SparcRegisterInfo.td The patch adds missing registers and instructions to complete all the registers supported by the Sparc v8 manual. 2016-02-27 12:49:59 +00:00
SparcSchedule.td [Sparc][LEON] Add UMAC and SMAC instruction support for Sparc LEON subtargets 2016-05-09 11:55:15 +00:00
SparcSubtarget.cpp [Sparc] Leon errata fix passes. 2016-07-08 15:33:56 +00:00
SparcSubtarget.h [Sparc] Leon errata fix passes. 2016-07-08 15:33:56 +00:00
SparcTargetMachine.cpp [Sparc] Leon errata fix passes. 2016-07-08 15:33:56 +00:00
SparcTargetMachine.h [Sparc][LEON] LEON Erratum fix. Insert NOP after LD or LDF instruction. 2016-05-23 10:56:36 +00:00
SparcTargetObjectFile.cpp
SparcTargetObjectFile.h
SparcTargetStreamer.h

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Use %g0 directly to materialize 0. No instruction is required.